Plug &amp; play I/sub DDQ/ monitoring with QTAG

Baker, K.; Waayers, Tom; Bouwman, F.; Verstraelen, M.

doi:10.1109/test.1995.529905

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…After transient period, the power supply current is negligible (a few or less µA) and this current is known as I DDQ . I DDQ current for a typical defective VLSI circuit is up to 1 mA [6]. So the sensor should be able to sense the quiescent current with precision.…”

Section: Currentmentioning

confidence: 99%

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Design of a Current Sensor for IDDQ Testing of CMOS IC

Ali¹,

Khamis²

2005

American J. of Applied Sciences

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This study presents the design of an off-chip current sensor for I DDQ testing of CMOS (Complementary Metal-oxide Semiconductor) ICs (integrated circuit). It provides a linear voltage signal of I DDQ current with a conversion factor of 5 mV/µA without any amplification. A voltagecontrolled switch is used to bypass the transient current peaks. It has also been shown that the sensor is capable of detecting I DDQ faults of a circuit at 100 kHz test frequency without degrading its performance.

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Section: Currentmentioning

confidence: 99%

“…It should be noted that in real hardware the sensor should be within a few millimeter of the DUT. This is to minimize the parasitic inductance and to optimize the decoupling system [6]. Otherwise the measurement frequency and the accuracy of the sensor may be affected.…”

Section: Design Of the Sensormentioning

confidence: 99%

Design of a Current Sensor for IDDQ Testing of CMOS IC

Ali¹,

Khamis²

2005

American J. of Applied Sciences

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A BIST-DFT technique for DC test of analog modules

Dufaza

Ihs

1996

J Electron Test

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Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-In Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.

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An off-chip current sensor for IDDQ testing of CMOS ICs

Altaf‐Ul‐Amin¹,

Darus

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

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Plug & play I/sub DDQ/ monitoring with QTAG

Cited by 3 publications

References 14 publications

Design of a Current Sensor for IDDQ Testing of CMOS IC

Design of a Current Sensor for IDDQ Testing of CMOS IC

A BIST-DFT technique for DC test of analog modules

An off-chip current sensor for IDDQ testing of CMOS ICs

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