Polysilicon-germanium gate patterning studies in a high density plasma helicon source

Abstract

High density plasma etching processes using halogen based chemistries have been studied for 0.2 μm polysilicon-germanium gate patterning. Bilayer gate stacks consisting of 80 nm polycrystalline Si on 120 nm polycrystalline Si1−xGex (x was varied between 0.55 and 1) were grown on 4.5 nm SiO2 covered 200 mm diameter p-type silicon wafers. The bilayer gates were masked with oxide patterns. The wafers were etched in a low pressure, high density plasma helicon source. Various mixtures, based on Cl2, HBr, and O2 gases, have been used to investigate the etching of the Si/SiGe bilayer gates. The gas mixture and the plasma operating conditions have been optimized to obtain anisotropic etching profiles for features down to 0.2 μm, and to minimize the gate oxide consumption. Real time process control was achieved using HeNe ellipsometry in blanket areas, allowing the SiGe/oxide transition to be easily detected. A two step etching process using a Cl2/O2–He mixture was developed. The first step uses a high energy ion bombardment in order to obtain a high etch rate, and the second step uses a lower ion energy to achieve high SiGe/oxide selectivity. The second step is started 40 nm before reaching the SiGe/SiO2 interface in order to reduce gate oxide consumption and structural defects formation at the edges of the gate.

Real-time ultraviolet ellipsometry monitoring of gate patterning in a high-density plasma

“…For Si/SiGe the etching time before end point is shorter, due to the higher etch rate of SiGe alloys compared to Si. 12 The Si/SiGe transition is not detected, as the refractive indices of these materials are very close at this wavelength ͑3.1 for poly Si, 3.0 for poly Si 0.25 Ge 0.75 ). The overetch step was started at mark OE, when ⌿ becomes stable.…”

“…We have recently developed a two-step process for 0.2 m Si/SiGe gate patterning using a Cl 2 /O 2 gas mixture. 12 The first step uses a high-energy ion bombardment in order to obtain a high etch rate, and the second one, a lower ion energy to achieve high SiGe/SiO 2 selectivity. The second step was started 40 nm before reaching the SiGe/oxide interface in order to reduce gate-oxide consumption and structural-defect formation at the edges of the gate.…”

High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates

“…Above 50% Ge, the impurity activation is so low that the material becomes virtually unusable as an n-type conductor. Additionally, there are increasing deviations from the standard Si MOS processing regarding gate etching, post-etch oxidation [11] as soon as the Ge mole fraction exceeds 0.5. On the other hand, at 20% Ge in the poly-gate the n-type gate activation properties are at least as good as those of poly-Si [19] and PMOS performance can be significantly improved (see previous section).…”

“…Recently, there have been quite a number of reports on the properties of heavily doped poly-SiGe films [2]- [6], [11]- [13].…”

“…Increase in Ge percentage results in an increase of the etching rate (up to times for 70% Ge as compared to poly-Si) which can hamper the uniformity of the etched profiles across the wafer for gates with high Ge content. In this regime (above % Ge) a specially developed etching chemistry should be used [11].…”