Post-layout leakage power minimization based on distributed sleep transistor insertion

Abstract

ABSTRACT

An effective state-based predictive approach for leakage energy management on embedded systems

“…Body-bias-based techniques can be combined with a sleep transistor to obtain further leakage power savings [21]. As power gating can effectively control leakage power, a lot of power-gating-based techniques have been proposed in recent work [3,4,6,20,27,33,41,46].…”

“…With its effectiveness in controlling leakage power, a lot of power-gating-based techniques have been proposed in recent work [3,4,6,20,21,27,33,41,46]. To effectively apply power gating, one of most important problems is how to predict the sufficiently long idleness of functional units.…”

Sleep transistor distribution in row-based MTCMOS designs

“…In these methods, all cells in a row share all of the STCs and the virtual ground line in the same row. The main advantages of these approaches are that (a) they are fully compatible with the existing standard-cell physical design flow and (2) they result in a shorter reactivation time when exiting the sleep state [16]. However, these approaches do not consider the voltage drop due to the virtual ground interconnect in deciding the location of STCs.…”

An MTCMOS technology for low-power physical design

“…Also Anis et al [10] and Babighian et al [12] have proposed postlayout gate clustering, and sizing methods, and put the physical location of gates into cost function. But there are still three disadvantages for the indirect minimization of virtual ground network after traditional placement.…”

“…Low-power design in the post-layout level mainly includes the fixed-row-based sleep transistors' placement [10,12]. These lowpower post-layout design methods first obtain the physical location of gates from existing physical design tools without considering the virtual supply networks minimization, and then put this physical information into cost function to place sleep transistors.…”