ABSTRACT

Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a synthesis-based design flow poses the challenge of interfacing logic blocks in shutdown mode with active units: The outputs of inactive gates can float at intermediate voltages, causing very large short-circuit currents in the active gates they drive. In this paper, we propose two novel low-overhead elementary cells that fully address this issue. These cells can be added to any synthesis library, and they can be inserted into a netlist at the boundary between shutdown and active regions. Our results show that: (i) Our cells solve the interfacing problem with minimum overhead; (ii) A nonintrusive design flow enhancement is sufficient to automatically insert interface cells in post-synthesis netlists.

No abstract

The BEOL compatible on-chip MIM capacitors have natural topography post MIM processing. In foundry manufacturing, design-related non uniform pattern density combined with MIM processing can lead to localized topographic process weak points. These weak points add further complexity and reduce the process window available to accommodate both MIM capacitors and Cu interconnections. The related fail modes include punch-through of MIM capacitors, un-landed Cu interconnection vias, and shorted Cu lines above the MIM capacitors. These challenges and complexities are described and characterized in this paper, as well as experiments and solutions to overcome these challenges. Manufacturing capability of BEOL MIM capacitors with capacitance density >20fF/µm 2 , leakage current density <100nA/cm 2 , and breakdown voltage > 5V has been demonstrated.

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