Post-route gate sizing for crosstalk noise reduction

Becer, M.; Blaauw, David; Algor, Ilan; Panda, Rajendran; Oh, Chang-Hwan; Zolotov, Vladimir; Hajj, I.N.

doi:10.1145/776067.776071

Cited by 4 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The coupling information can be completely extracted after detailed routing. The typical techniques to reduce the coupling capacitance include buffer insertion [Alpert et al 1998;Zhang and Sapatnekar 2004], wire permutation [Gao and Liu 1993], wire perturbation [Saxena and Liu 1999], wire shielding [Rabaey 1996], wire sizing [Jiang et al 2000], and gate sizing [Hashimoto et al 2002;Becer et al 2003;Jiang et al 2000;. Since wire and gate sizing can be done by incremental changes, they are suitable for post-layout optimization.…”

Section: Introductionmentioning

confidence: 99%

Reliable crosstalk-driven interconnect optimization

Jiang

Pan

Chang

et al. 2006

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

As technology advances apace, crosstalk becomes a design metric of comparable importance to area and delay. This article focuses mainly on the crosstalk issue, specifically on the impacts of physical design and process variation on crosstalk. While the feature size shrinks below 0.25μ m , the impact of process variation on crosstalk increases rapidly. Hence, a crosstalk insensitive design is desirable in the deep submicron regime. In this article, crosstalk sensitivity is referred to as the influence of process variation on crosstalk in a circuit. We show that the lower bound of crosstalk sensitivity grows quadratically, while that of crosstalk increases linearly. Therefore, designers should also consider crosstalk sensitivity, when optimizing other design objectives such as crosstalk, area, and delay. According to our modeling, these objectives are all in posynomial forms, and thus the multi-objective optimization problem can optimally be solved by Lagrangian relaxation. Experimental results show that our method is effective and efficient. For instance, a circuit of 2856 gates and 5272 wires is optimized using 13-minute runtime and 2.8-MB memory on a Pentium III 1.0 GHz PC with 256-MB memory. In particular, by relaxing Lagrange multipliers to the critical paths, it takes only two iterations for all solutions to converge to the global optimal, which is much more efficient than related previous work. This relaxation scheme provides a key insight into the rapid convergence in Lagrangian relaxation.

show abstract