Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization

Hanchate, N.; Ranganathan, N.

doi:10.1109/isqed.2006.101

Cited by 6 publications

(2 citation statements)

References 16 publications

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“…Several capacitance extraction methods exist ranging from simple analytical expressions to filed solver techniques and statistical techniques. In this work we use capacitance formulas introduced in [17] for two and three parallel lines. Fig.2 shows the schematic of parasitic capacitances along with the notations used for wire width, wires spacing and wire thickness.…”

Section: Interconnect Delay and Crosstalk Modelsmentioning

confidence: 99%

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Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization

Hasani

Masoumi

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate crosstalk reduction techniques which helps to have simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The optimization problem is modelled by solving a new cost function to find a minimum cost for both crosstalk noise and delay which are conflicting in nature. Through MATLAB software, a system of three coupled wires is modelled as a RC distributed network. The results indicate the number of optimum available solutions including wire sizing, wire spacing and buffer insertion in which crosstalk reduction techniques can be useful for both crosstalk noise and delay.

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Section: Interconnect Delay and Crosstalk Modelsmentioning

confidence: 99%

“…On the other hand, placement plays an important role on (7) the wire length. Also timing driven placement methods are very useful methods in delay optimization of timing critical nets [17]. Therefore placement synthesis and mapping should be considered during synthesis and technology mapping.…”

Section: Amentioning

confidence: 99%