Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology

IET Circuits, Devices & Syst

Rawat

Agarwal

2017

Self Cite

A 10-bit pipelined analogue-to-digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal-oxidesemiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) nwell technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge-pump-based concept that avoids the use of power-area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal-oxide-semiconductor field-effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area-power-cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential nonlinearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non-linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.

“…It shows that the DNL decreases with the increase in

A_{0}

for both the cases. However for the same

A_{0}

, DNL in the present work is about a half of that in the opamp‐based pipelined ADC due to unity feedback factor in the former [20]. Therefore, for the same DNL it requires lesser

A_{0}

and hence requires lesser power.…”

Section: Design Considerations and Optimisationmentioning

confidence: 73%

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

IET Circuits, Devices & Syst

Rawat

Agarwal

2017

Self Cite

“…This work focuses on the problem of gain error correction in 1.5-bit/stage pipelined ADC architecture using a digital calibration technique that can also be extended to other multi-bit pipelined ADC architectures. [18]. Achieving such a high gain would require more area and power.…”

Section: Non-idealities Analysis Of Pipelined Adcmentioning

confidence: 99%

“…However, in reality, a stage may suffer from various non‐idealities such as low open‐loop gain of op‐amp, incomplete settling, and capacitor mismatch. These errors deviate the interstage gain ( G ) from its ideal value of 2 and results in erroneous residue voltage as given by [18]

V_{res i} ≃ ()(, 1 - \frac{1}{A β}) ()(, 1 - e^{- t . UGB}) (][, ()(, 2 + normalΔ) V_{in i} - ()(, 1 + normalΔ) V_{dac i})

…”

Section: Non‐idealities Analysis Of Pipelined Adcmentioning

confidence: 99%

See 1 more Smart Citation

Fast digital foreground gain error calibration for pipelined ADC

Kaur¹,

Prabhakar

IET Circuits, Devices & Systems

et al. 2019

Self Cite

Here, a fast digital foreground calibration technique to calibrate the gain error in the pipelined analogue-to-digital converter (ADC) is proposed. The technique suggested uses maximum reference value of the ADC along with least mean squares adaptive algorithm to compensate the gain error. It avoids the use of slow but accurate reference ADC, thus saving area, power, and design efforts. The proposed calibration algorithm is implemented in Xilinx Artix-7 FPGA kit to show the effectiveness of the algorithm. After calibration, differential non-linearity improves by 30% and integral non-linearity reduces from values +60/−60 LSB to +0.77/-0.77 LSB. Also, signal to noise and distortion ratio and spurious-free dynamic range improve significantly from 35.9193 and 36.7348 to 75.3619 and 82.2884 dB, respectively, after calibration.

“…Summer provides the average of the external inputs and a feedback signal V f coming from the CM extractor block whichis stored in a capacitor

C_{f}

for summing. The capacitor

false(C_{f} false)

in the feedback block has been implementedby metal‐oxide‐semiconductor capacitor (MOSCAP) (metal–oxide–semiconductorfield‐effect transistor capacitor) [14–16]. A MOSCAP requiresless area, lesser number of fabrication mask layers and offers more capacitivedensity as compared to other monolithic capacitors such as MIMCAP (metalinsulator metal capacitor) or MOMCAP (metal oxide metal capacitor) or PIPCAP(polyinsulator polycapacitor) and so on.…”

Section: Flash Adc Architecturementioning

confidence: 99%

Highly‐digital voltage scalable 4‐bit flash ADC

Gupta

IET Circuits, Devices & Systems

Agarwal

2018

Self Cite

This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.