2005
DOI: 10.1007/s11265-005-6252-4
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Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

Abstract: When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the requ… Show more

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Cited by 5 publications
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“…Because of the unique characteristics of the memory circuit and layout, the power and substrate noise may cause functional failures. Making embedded memories noise-tolerant will be vital to a successful SoC design [17].…”
Section: Embedded Memorymentioning
confidence: 99%
“…Because of the unique characteristics of the memory circuit and layout, the power and substrate noise may cause functional failures. Making embedded memories noise-tolerant will be vital to a successful SoC design [17].…”
Section: Embedded Memorymentioning
confidence: 99%