Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application

Lambrechts, Andy; Raghavan, Praveen; Leroy, Anthony; Talavera, Guillermo; Aa, Tom Vander; Jayapala, Murali; Catthoor, F.; Verkest, D.; Corporaal, Henk; Robert, Frédéric; Carrabina, Jordi

doi:10.1109/asap.2005.52

Cited by 27 publications

(16 citation statements)

References 17 publications

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“…In other studies, it has been observed that in Motorola's M.CORE architecture, the register file contributes up to 42% of data path power dissipation and 16% of the total power consumption, and in Blackfin processor [25] the register file, per se, consumes 20% of the total processor core power consumption. In a Network-on-Chip (NOC) platform it has been observed that register file power consumption can reach to almost 37% of the total system while executing multimedia applications [23]. Even on the more recent processor microarchitecture, the 32 nm Westmere (WSM) core [45], which is used on mobile, desktop and servers, register files contribute to 30% of both dynamic and leakage power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Dynamically adaptive register file architecture for energy reduction in embedded processors

Tavana

Khameneh

Goudarzi

2015

Microprocessors and Microsystems

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Section: Introductionmentioning

confidence: 99%

Dynamically adaptive register file architecture for energy reduction in embedded processors

Tavana

Khameneh

Goudarzi

2015

Microprocessors and Microsystems

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“…Moreover, very recently it has been found that in new proposed embedded platforms with several processing elements, the shared register file plays a very important role as part of the memory subsystem and it can heavily affect the cycle time and consumes a very significant portion of the aforementioned percentage of the total energy consumed by the memory hierarchy [4]. Furthermore, it has become one of the critical processor hot-spots, specially for VLIW architectures, as [8] have shown. The main reasons are similar to those found in other layers of the memory subsystem.…”

Section: Introductionmentioning

confidence: 99%

Compiler-Driven Leakage Energy Reduction in Banked Register Files

Atienza

Raghavan

Ayala

et al. 2006

Lecture Notes in Computer Science

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Abstract. Tomorrow's embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embedded architectures.

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“…Moreover, very recently it has been found that in new proposed embedded platforms with several processing elements, the shared register file plays a very important role as part of the memory subsystem and it can heavily affect the cycle time and consumes a very significant portion of the aforementioned percentage of the total energy consumed by the memory hierarchy (Texas Instruments, 2004). Furthermore, it has become one of the critical processor hotspots, especially for VLIW architectures, as Lambrechts et al (2005) have shown. The main reasons are similar to those found in other layers of the memory subsystem.…”

Section: Introductionmentioning

confidence: 99%

Energy-aware compilation and hardware design for VLIW embedded systems

Ayala

López‐Vallejo

Atienza

et al. 2007

IJES

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Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management severely affects system power. In this paper, we present a new approach to reduce the energy of shared register files in forthcoming embedded VLIW processors running real-life applications up to 60% without performance penalty. This approach relies on limited hardware extensions and a compiler-based energy-aware register assignment algorithm to deactivate at run-time parts of the register file (i.e., sub-banks) in an independent way.

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Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application

Abstract: Abstract

Cited by 27 publications

References 17 publications

Dynamically adaptive register file architecture for energy reduction in embedded processors

Dynamically adaptive register file architecture for energy reduction in embedded processors

Compiler-Driven Leakage Energy Reduction in Banked Register Files

Energy-aware compilation and hardware design for VLIW embedded systems

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