Power constrained design of multiprocessor interconnection networks

Patel, C.S.; Chai, Sek; Yalamanchili, Sudhakar; Schimmel, D.E.

doi:10.1109/iccd.1997.628902

Cited by 64 publications

(25 citation statements)

References 7 publications

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“…Previous work [21] considered how power may reduce interconnection networks' capacity. There have been several prior efforts to reduce power in interconnection networks with a particular focus on reducing power on infrequently used links.…”

Section: Related Workmentioning

confidence: 99%

Active Measurement of the Impact of Network Switch Utilization on Application Performance

Casas

Bronevetsky

2014

2014 IEEE 28th International Parallel and Distributed Processing Symposium

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Abstract-Inter-node networks are a key capability of HighPerformance Computing (HPC) systems that differentiates them from less capable classes of machines. However, in spite of their very high performance, the increasing computational power of HPC compute nodes and the associated rise in application communication needs make network performance a common performance bottleneck. To achieve high performance in spite of network limitations application developers require tools to measure their applications' network utilization and inform them about how the network's communication capacity relates to the performance of their applications.This paper presents a new performance measurement and analysis methodology based on empirical measurements of network behavior. Our approach uses two benchmarks that inject extra network communication. The first probes the fraction of the network that is utilized by a software component (an application or an individual task) to determine the existence and severity of network contention. The second aggressively injects network traffic while a software component runs to evaluate its performance on less capable networks or when it shares the network with other software components. We then combine the information from the two types of experiments to predict the performance slowdown experienced by multiple software components (e.g. multiple processes of a single MPI application) when they share a single network. Our methodology is applied to individual network switches and demonstrated taking 6 representative HPC applications and predicting the performance slowdowns of the 36 possible application pairs. The average error of our predictions is less than 10%.

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Section: Related Workmentioning

confidence: 99%

Active Measurement of the Impact of Network Switch Utilization on Application Performance

Casas

Bronevetsky

2014

2014 IEEE 28th International Parallel and Distributed Processing Symposium

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“…At the architecture level, Patel et al [20] first proposed a power model for interconnection networks, deriving its power estimates based on transistor count. As the model is not instantiated with architectural parameters, it cannot be used to explore tradeoffs in router microarchitecture design.…”

Section: Related Workmentioning

confidence: 99%

Interference assisted lithography for patterning of 1D gridded design

Greenway¹,

Hendel

Jeong

et al. 2009

Alternative Lithographic Technologies

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As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, earlystage estimation of NoC power has become crucially important. ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes -the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip -we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validation against the two Intel chips confirms a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [23] confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.

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“…Interconnection networks: Substantial research has explored power consumption issues in interconnection networks. Patel et al [15] first developed power modeling techniques for routers and links. Wang et al [28] developed an architecture-level power model, called Orion, for interconnection networks.…”

Section: Discussion and Related Workmentioning

confidence: 99%

“…Therefore, we see addressing of on-chip network thermal issues providing valuable insights for managing entire on-chip systems. For networks, recent studies mainly focus on power issues, including modeling and characterization [10,15,28], design [27], and management [11,20]. Even though both power and temperature are a function of the communication traffic, the network thermal and power consumption profiles exhibit different run-time behavior.…”

Section: Introductionmentioning

confidence: 99%