Power constraint scheduling of tests

Chou, Ryan; Saluja, Kewal K.; Agrawal, Vishwani D.

doi:10.1109/icvd.1994.282700

Cited by 68 publications

(25 citation statements)

References 10 publications

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“…Obviously, these three tests must not be scheduled for concurrent execution. This fact and informal statements of results appear in a preliminary version of this paper [4].…”

Section: Background and Preliminariesmentioning

confidence: 75%

Scheduling tests for VLSI systems under power constraints

Chou

Saluja

Agrawal³

1997

IEEE Trans. VLSI Syst.

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240

243

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Abstract-This paper considers the problem of testing VLSI integrated circuits in minimum time without exceeding their power ratings during test. We use a resource graph formulation for the test problem. The solution requires finding a power-constrained schedule of tests. Two formulations of this problem are given as follows: 1) scheduling equal length tests with power constraints and 2) scheduling unequal length tests with power constraints. Optimum solutions are obtained for both formulations. Algorithms consist of four basic steps. First, a test compatibility graph is constructed from the resource graph. Second, the test compatibility graph is used to identify a complete set of time compatible tests with power dissipation information associated with each test. Third, from the set of compatible tests, lists of power compatible tests are extracted. And finally, minimum cover table approach is used to find an optimum schedule of power compatible tests.

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“…Obviously, these three tests must not be scheduled for concurrent execution. This fact and informal statements of results appear in a preliminary version of this paper [4].…”

Section: Background and Preliminariesmentioning

confidence: 75%

Scheduling tests for VLSI systems under power constraints

Chou

Saluja

Agrawal³

1997

IEEE Trans. VLSI Syst.

Self Cite

240

243

View full text Add to dashboard Cite

show abstract

“…The drawbacks of this approach are the area overhead and the performance degradation that it incurs, as well as the negative impact on the design flow. Some other solutions have been proposed recently to cope with the power problem during scan testing including low power ATPGs [9,29], a scan path segmentation technique [25,30], a static compaction technique [23], two clock scheme modification techniques [2,24], an interleaving scan architecture for multiple-scan circuits [20], a test data compression technique for SOC [7], test scheduling techniques [8,18].…”

Section: Introductionmentioning

confidence: 99%

Power-Driven Routing-Constrained Scan Chain Design

et al. 2004

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Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.

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“…A test generation technique for low power, has been discussed in [3]. Another approach is based on scheduling so that during testing, maximum power consumption is kept under a certain threshold to avoid burning the DUT [4]. Previous works ( [5] [6] [7]) have also suggested reordering of test vectors so that the Hamming distance between adjacent vectors is minimal.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of heuristic techniques for test vector ordering

Hashempour

Lombardi

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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Vector reordering is an essential task in testing VLSI systems because it affects this process from two perspectives: power consumption and correlation among data. The former feature is crucial and if not properly controlled during testing, may result in permanent failure of the device-under-test (DUT). The latter feature is also important because correlation is captured by coding schemes to efficiently compress test data and ease memory requirements of Automatic-TestEquipment (ATE), while reducing the volume of data and lowering the test application time. Reordering however is NP-complete. This paper presents an evaluation of different heuristic techniques for vector reordering using ISCAS85 and ISCAS89 benchmark circuits in terms of time and quality. For this application, it is shown that the best heuristic technique is not the famous Christofides or Lin-Kernighan, but the Multi-Fragment technique.

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Power constraint scheduling of tests

Cited by 68 publications

References 10 publications

Scheduling tests for VLSI systems under power constraints

Scheduling tests for VLSI systems under power constraints

Power-Driven Routing-Constrained Scan Chain Design

Evaluation of heuristic techniques for test vector ordering

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