Power consumption in fast dividers using time shared TMR

Gallagher, W.L.; Swartzlander, Earl E.

doi:10.1109/dftvs.1999.802892

Cited by 3 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, these faults must be detected during the operation of the circuit. Generally, transient faults can be detected by self-checking circuits, [5][6][7][8][9] built-in fault detection, and correction circuits [10][11][12][13][14][15][16][17][18][19][20][21] . By using the built-in fault detection and correction circuits, the transient faults can be tolerated during the run time.…”

Section: Introductionmentioning

confidence: 99%

“…[10][11][12][13][14][15][16][17][18][19][20][21] . The recomputing with circularly shifted operands (RECO) technique was applied to multipliers to detect errors during the run time.…”

Section: Introductionmentioning

confidence: 99%

“…In a previous study, a TMR technique combined with a time-shared method (TSTMR) was used to reduce circuit area. 19 An alternative fault-tolerant multiplier using a partitioning technique was presented in Ref. 20.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Multi-Stage Fault-Tolerant Multiplier With Triple Module Redundancy (Tmr) Technique

Chen

Shyu

et al. 2014

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

In this study, a multistage fault-tolerant (MSFT) scheme for two¯xed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost faulttolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-m CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 Â 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 Â 64 Type-I MSFT multiplier is only 0:21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 Â 64 Type-II MSFT multiplier

show abstract

Section: Introductionmentioning

confidence: 99%

“…[10][11][12][13][14][15][16][17][18][19][20][21] . The recomputing with circularly shifted operands (RECO) technique was applied to multipliers to detect errors during the run time.…”

Section: Introductionmentioning

confidence: 99%