Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits

Shapiro, Alexander E.; Friedman, Eby G.

doi:10.1109/tvlsi.2015.2409051

Cited by 24 publications

(13 citation statements)

References 10 publications

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“…The research is being carried out at different levels to improve the power reduction techniques and to improve the low power design circuits [3]. Another method to solve the power consumption problem is by using the multi supply voltage domain techniques [4] where the voltage level depends on the time and requirement. To maximize the performance time critical domains are driven at high power supply voltages and for low power supply voltages non critical sections will drive to increase the power efficiency [2].…”

Section: Literature Surveymentioning

confidence: 99%

“…In a similar attempt Shapiro and Friedman proposed a power efficient level shifter using FinFET using 16 nm technologies for the near threshold circuits. This level shifter is capable of level shifting the voltages from 250 mV to 790 mV with a 42% shorter delay at a very low energy consumption of 45% and with low static power dissipation of 48% [4].…”

Section: Literature Surveymentioning

confidence: 99%

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High Speed Level Shifters for Low Power Applications with Reduced Size

2018

IJRTER

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-In this paper a high speed level shifter is proposed for low power applications. This circuit is a power efficient level shifter that converts low level input voltages to high level voltages as per the design requirement. The efficiency of pull up and pull down transistors are improved in the proposed method and the circuit was tested by using 180 nm CMOS technology. A unit buffer and inverter circuit was introduced to the load circuits and input buffers to have fair comparison between different structures. The overall power consumption in the proposed circuit was reduced to a minimum level by reducing the number of transistors to build a level shifter.

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Section: Literature Surveymentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

High Speed Level Shifters for Low Power Applications with Reduced Size

2018

IJRTER

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“…It is widely used in multi-rail power supply on-chip systems, such as Very Large Scale Integration circuit (VLSI), Micro-Electro-Mechanical Systems (MEMS), mixed-signal integrated circuits and power-conversion systems [1][2][3][4][5][6][7][9][10][11][14][15][16][17][18][20][21][22][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

“…For low voltage applications [3,10,20,25,26], with the supply voltage of logic circuit decreasing to subthreshold while the supply voltage of analog circuit remains unchanged, level shifter comes across new challenges [3]. The conventional level shifter design based on differential cascode voltage switch topology is limited for robust up-conversion from sub-threshold to super-threshold.…”

Section: Introductionmentioning

confidence: 99%

“…This is due to the significant current contention caused by the limited driving strength of the pull-down devices operating in the sub-threshold region. The existing methods to solve this problem are, (a) decreasing the driving strength of pull-up devices by adding current limitation structures [20] or increasing the driving strength of pull-down devices by reducing threshold [20]; (b) converting the sub-threshold signal to the superthreshold signal by a boosting capacitor [10]; (c) employing a differential amplifier to take advantage of its high voltage gain instead of traditional differential cascode voltage switch structures [26]. Other level shifter applications [1,9,21] include its use along with switch capacitor circuit to compensate operational amplifiers.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

Lai

Zhong

et al. 2017

Circuits Syst Signal Process

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In this paper, a new high-voltage level shifter (HVLS) structure is proposed, which has a significantly improved transient response over existing structures. To overcome signal transfer delay of the conventional HVLS caused by parasitic capacitance due to high-voltage MOSFETs, this structure employs a novel circuit module "inverse Schmitt trigger" to drive the pull-up transistors of conventional HVLS. As a result, the "Miller Plateau" caused by parasitic capacitance can be minimized. Hence, the overall transfer delay of the structure is significantly reduced. The simulation results based on SPECTRE and 0.5μm high-voltage CMOS process show that compared to other currently available structures whose transfer delays are several nanoseconds on average, the proposed structure is able to provide a nanosecond transfer delay without using large boost capacitors which are impractical to be integrated or using complex logic units which decrease reliability of circuit. Also, the typical transfer delay of the proposed structure is a constant 1.3ns, which is irrelevant to parasitic capacitance and insensitive to transfer voltage level.

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Power‐efficient voltage up level shifter with low power–delay product

Fayaz

Rao

2021

Circuit Theory & Apps

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SummaryIn this article, a power‐efficient hybrid voltage up level shifter (LS) is designed. By using a combination of a current mirror (CM) and a cross‐coupled pMOS pair in a pull‐up circuitry, the dynamic power is reduced significantly even at boosted switching speed. The designed LS circuit, which occupies a small silicon area, consists of 10 transistors and is mainly suitable for ultra‐low‐power applications, such as wireless sensor nodes and biomedical appliances. Moreover, it can convert extreme low‐level input voltages to the high supply voltage levels. The results obtained from post‐layout simulations in a standard 180‐nm CMOS process illustrate that the designed LS circuit has total power consumption, static power dissipation, and propagation delay of 33.93 nW, 253 pW, and 9.09 ns, respectively, at 1 MHz with a minimum supply voltage (VDDL) of 0.4 V and nominal supply voltage (VDDH) of 1.8 V. Also, the designed LS can convert an input voltage of 0.12–1.8 V at 10 kHz.

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Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits

Cited by 24 publications

References 10 publications

High Speed Level Shifters for Low Power Applications with Reduced Size

High Speed Level Shifters for Low Power Applications with Reduced Size

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

Power‐efficient voltage up level shifter with low power–delay product

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