Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level

Abstract

Abstract. In current multimedia applications like 3D graphical processing or games, the run-time memory management support has to allow real-time memory de/allocation, retrieving and data processing. The implementations of these algorithms for embedded platforms require high speed, low power and large data storage capacity. Due to the large hardware/software co-design space, high-level implementation cost estimates are required to avoid expensive design modifications late in the implementation. In this paper, we present an approach designed to do that. Based on memory accesses, normalised memory usage 1 and power estimates, the algorithm code is refined. Furthermore, optimal implementations for the dynamic data types involved can be selected with a considerable power contribution reduction.

Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems

“…After implementing and profiling these two generic DM managers, we have observed that most of the accesses in Kingsley occur in just few of the "bins" (or memory pools of the heap) [15], due to the limited range of data type sizes used in the application [5]. Therefore, we try to reduce its memory waste by modifying its design with our layers and by limiting the number of bins to the actual sizes used in the application (5 main sizes), as Figure 4 shows at the top in its right graph.…”

“…Since more than one layer can constitute the part of the manager to measure, the profiling information must be grouped and cannot be collected at one layer only. Therefore, we have integrated a similar approach to the one proposed in [5] for complex dynamic data types. As Figure 3 depicts, it consists of an object-oriented profiling framework that decouples this information from the class hierarchy of the DM managers, providing accurate run time information on memory accesses, memory footprint, timing information and method calls.…”

“…They must rely on DM for a very significant part of their functionality due to the inherent unpredictability of the input data, which heavily influences global performance and memory footprint of the system. Designing them using static worst case memory footprint solutions would lead to a too high overhead in memory footprint and power consumption for these systems [5]. Also, power consumption has become a real issue in overall system design (both embedded and general-purpose) due to circuit reliability and packaging costs [14].…”

Custom Design of Multi-Level Dynamic Memory Management Subsystem for Embedded Systems

“…The first phase of our approach (number 1 in Figure 2) is an analysis of the run-time de/allocation and access behavior (i.e., reads and writes) of each DDT in the application under study. This is possible thanks to the use of our previous work, namely profiling tools for DDTs [10] and the exploration of custom DM managers [1]. The analysis of the first phase of our approach reveals the spatial (also temporal) locality of the DDTs in the dynamic application, which are mainly linked to the logical phases of the algorithms involved in the application (see Section 6 for real examples).…”

“…First, we compute the read and write accesses to the cache, scratchpad and main memory with the profiling data of: (i) the DDTs and (ii) the dynamic memory management mechanism as we explained in our previous work, i.e., [10] and [1] respectively. Next, to evaluate the cache hits and misses we use the very well known Dinero IV cache simulator [11].…”