Power minimization and technology comparisons for digital free-space optoelectronic interconnections

Abstract

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSEL's) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bitrate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSEL's and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 m down to 0.1 m brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 m CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm 2 can be achieved in an optimized free-space optical interconnect system using either VCSEL's or MQW modulators as its transmitters.

Rationale and challenges for optical interconnects to electronic chips

“…This has been considered by various authors as part of their analyses [8]- [11], [19]- [21], [26], [29], [30], [47], [58], [101]- [104]. We discuss some of the challenges in receiver design in Section III-A1.…”

“…[9], [26], [29]. An additional source of saving in power dissipation may be that we can avoid building resynchronization circuits (e.g., phase-locked loops, buffers), see Section II-C1.…”

“…Since that time, a body of work (see, for example, [4] and [6]- [33]) has addressed potential benefits and limits of optics for interconnection [4], [7], [8], [12], [14]- [16], [20], [23], [24], [28], analysis of the relative benefits of optics versus electronics [4], [6], [9]- [11], [13], [21], [22], [26], [27], [30], [31], [33], and comparison of different kinds of optical approaches against one another [17]- [19], [25], [29]. Several of these papers review parts of this work (e.g., [20], [22], [27], and [28]).…”

Power Efficiency Comparisons of Interchip Optical Interconnect Architectures

“…1(b)]. Power dissipation [12], [13] consists of static absorbed photocurrent and dynamic switching components, in addition to external laser power. The swing voltage V swing is assumed to be the nominal CMOS voltage supply V dd for the given technology, and the prebias voltage V bias is twice the supply voltage.…”

“…This brief uses current state-of-the-art and reasonable projected optical device parameters and leverages previous optimization methods for optical receiver design [10] and overall link design [11]- [13]. In addition, an optimal current density methodology with normalized transistor parameters extracted from circuit simulations is applied to jointly optimize driver and receiver circuitry to minimize the total link power dissipation.…”