This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSEL's) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bitrate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSEL's and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 m down to 0.1 m brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 m CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm 2 can be achieved in an optimized free-space optical interconnect system using either VCSEL's or MQW modulators as its transmitters.

High-performance polymer microlens arrays were fabricated by means of withdrawing substrates of patterned wettability from a monomer solution. The f-number (f(#)) of formed microlenses was controlled by adjustment of monomer viscosity and surface tension, substrate dipping angle and withdrawal speed, the array fill factor, and the number of dip coats used. An optimum withdrawal speed was identified at which f(#) was minimized and array uniformity was maximized. At this optimum, arrays of f/3.48 microlenses were fabricated with one dip coat with uniformity of better than Deltaf/f +/- 3.8%. Multiple dip coats allowed for production of f/1.38 lens arrays and uniformity of better than Deltaf/f +/-5.9%. Average f(#)s were reproducible to within 3.5%. A model was developed to describe the fluid-transfer process by which monomer solution assembles on the hydrophilic domains. The model agrees well with experimental trends.

We report a means of fabricating hydrophilic domains in a hydrophobic background by lithographically patterning an adhesive hydrophobic layer. Polymer microlenses were fabricated on these substrates by use of a dip-coating technique. Various lens shapes (circular, elliptical, square) were fabricated on a variety of substrates (SiO(2), SiN, GaAs, InP, etc.), ranging in size from 2 to 500 microm in diameter, with fill factors of up to 90%. Plano-convex and double-convex lenses were fabricated, with f-numbers as low as 1.38 and 1.2, respectively. Optimum lens surfaces deviated from spherical by just +/-5 nm . The lenses are stable at room temperature and exhibit minimal degradation after 24 h at 105 degrees C. The transfer of these polymer lenses to an underlying substrate was also demonstrated.

We present the theory, experimental results, and analytical modeling of high-speed complementary metal-oxide-semiconductor (CMOS) switches, with a twodimensional (2-D) layout, suitable for the implementation of packet-switched free-space optoelectronic multistage interconnection networks (MIN's). These switches are fully connected, bidirectional, and scaleable. The design is based on the implementation of a half-switch, which is a two-to-one multiplexer, using a 2-D layout. It introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5 V being the third value for a 5 V power supply. Simulations show that for a 0.8-m CMOS technology the switches can operate at speeds up to 250 Mb/s. Scaled-down versions of the switches have been successfully implemented in 2.0 m CMOS. The analytical modeling of these switches show that large scale free-space optoelectronic MIN's using this concept could offer close to Terabit/sec throughput capabilities for very reasonable power and area figures. For example, a 4096 channel system could offer 256 Gb/s aggregate throughput for a total silicon area of about 18 cm 2 and a total power consumption (optics plus electronics) of about 90 W.Index Terms-Analytical modeling of CMOS circuits, freespace optoelectronic interconnections, multistage interconnection networks, parallel systems, three-valued logic, two-dimensional layout, VLSI switches.

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