Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

Bardon, M. Garcia; Sherazi, Yasser; Jang, Doyoung; Yakimets, D.; Schuddinck, P.; Baert, Rogier; Mertens, Hans; Mattii, Luca; Parvais, B.; Mocuta, A.; Verkest, D.

doi:10.1109/vlsit.2018.8510633

Cited by 44 publications

(20 citation statements)

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“…All the parameters except NP and CPP are obtained from [9]. CPP is equivalent as in [12], and 16 nm in NP is calculated as the fin width (5 nm) subtracted from metal pitch (21 nm) in the sub-5-nm node [15]. Doping concentrations of S/D and punch-through-stopper are 2×10 20 and 2×10 18 cm -3 , respectively.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Yoon

Baek

2020

IEEE Access

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A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G m) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R o) by dual-WF scheme and thus achieve larger intrinsic gain (A V = G m R o). Smaller G m and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large R o increases the maximum frequency (F max). Especially, 2-CAS has larger A V and F max than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Yoon

Baek

2020

IEEE Access

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“…NWFETs are considered as a prospective candidate for continuation of transistor scaling because their geometry ensures better electrostatic channel control compared to the planar MOSFETs. e better scalability originates from technology reasons as the nanowire diameter could be well controlled to sizes below 10 nm [45].…”

Section: Nanowire and Nanosheet Transistorsmentioning

confidence: 99%

Technology and Modeling of Nonclassical Transistor Devices

Angelov

Nikolov

Hristov

2019

Journal of Electrical and Computer Engineering

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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“…Yu are with the School of Electrical Engineering, Korea University, Seoul 02841, Korea (e-mail: yuhykr@korea.ac.kr). layout area is required [6], [7]. Thus, to further reduce the area of devices in layout, lots of device structures like forksheet FET, complementary field-effect transistor (CFET) have been suggested [1]- [7].…”

Section: Introductionmentioning

confidence: 99%

“…In case of NARLab, they predict that CFET can improve CMOS inverter performances when compared to standard CMOS with NSHFETs, but there is no analysis on the reason [5]. However, prediction and analysis of CMOS inverter performances is crucial to ascertain the possibility of commercialization [6], [7].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

Jung

Jang

Min

et al. 2022

IEEE J. Electron Devices Soc.

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For the first time, by using 3-D TCAD, the advantage of using complementary FET (CFET), which has vertically stacked nanosheet nFET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CFET can increase the frequency by ~2.3% in iso-power and decrease power by ~7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by ~55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (Ceff) of the CFET compared to the standard CMOS. This low Ceff of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.

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Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

Cited by 44 publications

References 1 publication

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Technology and Modeling of Nonclassical Transistor Devices

Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

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