Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing

Liang, Chunyong; Wu, Mengfan; Huang, Jiun-Lang

doi:10.1109/ats.2010.68

Cited by 4 publications

(2 citation statements)

References 26 publications

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“…The automatic test equipment (ATE) which can supply speed clock is often expensive and the ordinary ATE cannot provide the high frequency clock. The design of at-speed scan test in this paper used the internal high speed clock generated by the chip [5] [6].…”

Section: Introductionmentioning

confidence: 99%

An on-Chip Clock Controller for Testing Fault in System on Chip

Lin¹,

Shi²

2013

Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)

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In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase-locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timingrelated defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

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Section: Introductionmentioning

confidence: 99%

An on-Chip Clock Controller for Testing Fault in System on Chip

Lin¹,

Shi²

2013

Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)

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“…Although combinational broadcast-scan-based test compression typically achieves lower compression ratios than the sequential linear-decompression-based architectures, it has great practical relevance due to its much simpler design, easy integration into standard ATPG flows and higher ATPG efficiency [16]. The X-filling method of [17] achieves a capture-power reduction in Illinois broadcast-scan architectures [18]. The approach requires addi-tional DFT hardware.…”

Section: Introductionmentioning

confidence: 99%

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Kochte¹,

Miyase²,

Wen³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.

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Broadcast test pattern generation considering skew-insertion and partial-serial scan

Lin

Huang

2011

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test

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Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing

Cited by 4 publications

References 26 publications

An on-Chip Clock Controller for Testing Fault in System on Chip

An on-Chip Clock Controller for Testing Fault in System on Chip

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Broadcast test pattern generation considering skew-insertion and partial-serial scan

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