Practical approaches to improve thermal SOA for smart power IC

Nitta, T.; Omichi, Akemi; Yanagi, S.; Yoshihisa, Y.; Kuroi, T.; Hatasako, K.; Maegawa, Satoru; Furuya, K.

doi:10.1109/ispsd.2011.5890861

Cited by 7 publications

(10 citation statements)

References 7 publications

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“…Without going into details, minority carrier injection prevention [9], thermal-SOA evaluation/ improvement [10], FPMOS current drivability enhancement [11], and pulse stress evaluation to SOI devices [12] have contributed to size reduction and the increased reliability.…”

Section: Soi Device Technologymentioning

confidence: 99%

Past and Future Technology for Mixed Signal LSI

Hatasako

Nitta

Hane

et al. 2014

IEICE Trans. Electron.

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SUMMARYThis paper discusses Mixed Signal LSI technology with embedded power transistors. Trends in Mixed Signal LSI technology are explained at first. Mixed signal LSI technology has proceeded with the help of fine fabrication technology and SOI technology. The BEOL transistor is a new development, which uses InGaZnO (IGZO) as its TFT channel material. The BEOL transistor is one future device which enables 3D IC and chip shrinking technology.

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Section: Soi Device Technologymentioning

confidence: 99%

Past and Future Technology for Mixed Signal LSI

Hatasako

Nitta

Hane

et al. 2014

IEICE Trans. Electron.

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“…Because LDMOS devices are usually operated under high drain voltage and high temperature conditions, such as in automotive applications, the stress-induced degradation becomes a major reliability issue in LDMOS transistors. [6][7][8][9][10][11] Most of reliability studied about STI-based LDMOS are focused on hot-carrier degradation, thus short of reliability information on high temperature stress degradation, especially for high temperature reverse bias (HTRB) stress mode, which is one of the most importance reliability issue in high voltage devices. 13) Moreover, the characterization technique and reliability degradation mechanism of LDMOSFETs differ substantially from standard CMOS devices due to the complex device architecture.…”

Section: Introductionmentioning

confidence: 99%

“…13) Moreover, the characterization technique and reliability degradation mechanism of LDMOSFETs differ substantially from standard CMOS devices due to the complex device architecture. [6][7][8][9][10][11] There is growing evidence that the presence of bulk and interface states is responsible for the degradation of the intrinsic electronic performance of LDMOSFETs. [12][13][14] Up to now, besides the traditional I d -V g method, some other characterization techniques, i.e., the charge-pumping (CP), 15) multiple level charge-pumping (MLCP) technique, 16,17) low-frequency 1/f noise, [18][19][20] and multi-region direct-current current-voltage (MR-DCIV) 21,22) technique have been developed for characterizing interface states in LDMOSFETs.…”

Section: Introductionmentioning

confidence: 99%

High temperature behavior of multi-region direct current current–voltage spectroscopy and relationship with shallow-trench-isolation-based high-voltage laterally diffused metal–oxide–semiconductor field-effect-transistors reliability

He¹,

Zhang²,

Zhang³

2014

Jpn. J. Appl. Phys.

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With the process compatibility with the mainstream standard complementary metal–oxide–semiconductor (CMOS), shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular for its better tradeoff between breakdown voltage and performance, especially for smart power applications. A multi-region direct current current–voltage (MR-DCIV) technique with spectroscopic features was demonstrated to map the interface state generation in the channel, accumulation and STI drift regions. High temperature behavior of MR-DCIV spectroscopy was analyzed and a physical model was verified. Degradation of STI-based LDMOS transistors under high temperature reverse bias (HTRB) stress is experimentally studied by MR-DCIV spectroscopy. The impact of interface state location on device electrical characteristics was investigated. Our results show that the major contribution to HTRB degradation, in term of the on-resistance degradation, was attributed to interface state generation under STI drift region.

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“…The increase in junction temperature (T j ) of the LDMOS is large and reaches more than 200 C, in highpower and DC operation. 5,6) This self-heating phenomenon of the LDMOS under high-power operation seriously affects the device degradation. [5][6][7] However, the upper limit of T j is about 150 C in the above application.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Hot Carrier Degradation of Lateral Double-Diffused Metal–Oxide–Semiconductor under Gate Pulse Stress

Furuya

Nitta

Katayama

et al. 2010

Jpn. J. Appl. Phys.

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The lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor is one of the key elements of high-power devices. It is difficult to evaluate the degradation of an LDMOS at the required temperature range, because the self-heating effect of an LDMOS is too large for conventional evaluation in DC. In this paper, we report on the hot carrier degradation of an LDMOS under high-power operation, by investigating the LDMOS deterioration in the case that both the device structure and junction temperature (T j) are different. The T j of an LDMOS is controlled by operating the gate voltage (V g) in pulse mode. Controlling T j by operating V g in pulse mode, the T j dependence of hot carrier degradation under high-power operation can be evaluated widely and quantitatively. The threshold voltage (V th) shift is observed according to the bias temperature mode irrespective of the device structure. On the other hand, the shift of drain current is affected by the length of the accumulation region under the gate electrode, and a relatively small increase in drain current (I ds) shift is observed with decreasing T j. These phenomena are clarified from the results of charge pumping measurement and simulation.

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Practical approaches to improve thermal SOA for smart power IC

Cited by 7 publications

References 7 publications

Past and Future Technology for Mixed Signal LSI

Past and Future Technology for Mixed Signal LSI

High temperature behavior of multi-region direct current current–voltage spectroscopy and relationship with shallow-trench-isolation-based high-voltage laterally diffused metal–oxide–semiconductor field-effect-transistors reliability

Analysis of Hot Carrier Degradation of Lateral Double-Diffused Metal–Oxide–Semiconductor under Gate Pulse Stress

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