Precision-aware soft error protection for GPUs

Abstract

With the advent of general-purpose GPU computing, it is becoming increasingly desirable to protect GPUs from soft errors. For high computation throughout, GPUs must store a significant amount of state and have many execution units. The high power and area costs of full protection from soft errors make selective protection techniques attractive. Such approaches provide maximum error coverage within a fixed area or power limit, but typically treat all errors equally. We observe that for many floating-point-intensive GPGPU applications, small magnitude errors may have little effect on results, while large magnitude errors can be amplified to have a significant negative impact. We therefore propose a novel precision-aware protection approach for the GPU execution logic and register file to mitigate large magnitude errors. We also propose an architecture modification to optimize error coverage for integer computations. Our approach combines selective logic hardening, targeted checker circuits, and intelligent register file encoding for best error protection. We demonstrate that our approach can reduce the mean error magnitude by up to 87% compared to a traditional selective protection approach with the same overhead.

Characterizing and Improving the Resilience of Accelerators in Autonomous Robots

“…Error Mitigation Techniques: There has been significant work on selective error mitigation techniques for CPUs [85] and GPUs [69], [72], [81]. Mittal et al [72] proposed compressing similar values in GPUs.…”

“…Mittal et al [72] proposed compressing similar values in GPUs. Palframan et al [81] analyzed GPGPU applications and proposed architectural modifications to reduce the magnitude of errors. Unfortunately, these methods are difficult to apply to MPAs due to differences in the ISA and microarchitecture.…”

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

“…Palframan et al [70] present a technique for improving reliability of GPUs. They note that for several floating-point intensive GPU applications, small magnitude errors have negligible effect on results while large magnitude errors may get amplified to have a significant negative impact.…”

A dynamic reconfiguration mechanism to increase the reliability of GPGPUs

“…In the past, BISR has been successfully applied in the memory blocks of processor-based systems by adding spare rows, columns, and additional controller structures to correct faults during the production phase and also during in-field execution [6,7]. Other works [8][9][10] targeted data-path units, such as the register file, and some internal components of the execution units (EUs) [11]. Similarly, some works proposed reconfiguration solutions targeting computational blocks in GPGPUs [12] or other modules in the GPGPU, such as the memories [13], and functional units [14], or combinations of both aligning the system to the specific workload requirements [2,15].…”