Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results

Chen, Baozhen; Maddox, Mark; Coln, Michael C. W.; Lü, Ye; Fernando, Lalinda D.

doi:10.1109/jssc.2018.2793558

Cited by 28 publications

(4 citation statements)

References 8 publications

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“…In recent years, with the rapid development of electronic technology and the massive application of integrated circuits, higher requirements for the reliability and stability of circuits and systems have been put forward, and the circuit system is required to detect key operating parameters quickly and accurately [1][2][3][4]. The high-power devices in integrated circuits cannot withstand short-time overloads and are prone to excessive energy accumulation in the tube due to overvoltage or overcurrent, which can lead to tube damage [5][6][7]. In practice, overcurrent protection circuits are often used to enable power devices' stable and reliable operation [8][9].…”

Section: Introductionmentioning

confidence: 99%

Design of reduced-current overcurrent protection circuit based on GBDT model

Wen

2023

Applied Mathematics and Nonlinear Sciences

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To address the problems of slow response and insufficient protection sensitivity of existing overcurrent protection techniques, this paper verifies the feasibility of the design of reduced-current overcurrent protection circuits by using the GBDT model. Firstly, the regression tree is used as a circuit learner for iteration, and the CART algorithm is applied to calculate circuit splitting characteristics and optimal splitting points to obtain the gain of splitting. Then the line loss rate is calculated using the differential evolution method to derive the objective function of the minimized line and the optimal value of the circuit. Finally, the mean value is extracted by calculating the optimal line’s statistical characteristics, the regression tree nodes are calculated using the GBDT model, and the root means the square error is used to verify the effectiveness of the circuit protection design proposed in this paper. The experimental results show that the overcurrent protection value of the circuit sample is around 1.35A and the current limit protection time is around 13ms by verifying the current reduction protection function and indication function of the circuit in the full temperature range. This shows that the GBDT model enables the reduced-current overcurrent protection circuit to perform timely and accurate overcurrent detection actions, and the circuit can be reliably protected under different overcurrent conditions.

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Section: Introductionmentioning

confidence: 99%

Design of reduced-current overcurrent protection circuit based on GBDT model

Wen

2023

Applied Mathematics and Nonlinear Sciences

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“…In the literature [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], several DAC designs have been presented to achieve low-power consumption in a small implementation area. Moreover, these designs are based on direct conversion from the digital domain to the analogue domain.…”

Section: Introductionmentioning

confidence: 99%

“…For DAC design, there are many implementation techniques such as resistor-string DAC [3], capacitor-resistor (C-R) DAC [4], charge redistribution DAC [5], cyclic DAC [6,7], charge scaling with split-capacitor array DAC [8,9], segmented DAC [10], current steering DAC [11], dual-capacitor array DAC [12], charge-sharing DAC [13,14], sigma-delta DAC [15], and pipelined DAC [16,17]. However, resistor-string DACs consume high power and occupy a large area.…”

Section: Introductionmentioning

confidence: 99%

A 0.002‐mm ² 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)

Hassan

Mostafa

Refky

et al. 2021

IET Circuits, Devices & Syst

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Digital-to-analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital-to-time converter (DTC) and a time-to-voltage converter (TVC), is employed to form a low-power time-based DAC (T-DAC) that fits low-power low-speed applications. This novel conversion mixes the digital input code into a digital pulse width modulated (D-PWM) signal through the DTC circuit, then converts this D-PWM signal into an analogue voltage through the TVC circuit. This new T-DAC is not only an energy-efficient design but also an area-efficient implementation. Power optimization is achieved by controlling the supply voltage of the TVC circuit with a discontinuous waveform using a low bias current. Moreover, the implementation area is optimized by proposing a new DAC architecture with a coarse-fine DTC circuit. Post-layout simulations of the proposed T-DAC is conducted using industrial hardware-calibrated 0.13 μm. Complementary metal oxide semiconductor technology with a 1 V supply voltage, 1 MS/s conversion rate, and 0.9 μW power dissipation.

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“…In particular, a Sample-wise Switched Reference Charge Reservoir (SS-RCR) technique was introduced [12], where a sufficiently large capacitor (reservoir), β times larger than the total bit capacitors, precharged to the reference voltage level during the sample phase acts as the reference for all bit switchings during the entire ADC. Very recently, a Bitwise Switched Reference Charge Reservoir (BS-RCR) technique was proposed [13], where the charge reservoir capacitor is split into the corresponding bit, and before each bit switching, the corresponding bit charge reservoir capacitor is precharged to the reference levels and used as the reference during each bit decision. With BS-RCRs, a 16-bit 1 MS/s SAR-ADC in 55 nm CMOS with 6.95 mW with a FoM of 738 fJ/conversion-step [14] and a 16-bit 16 MS/s SAR in 55 nm CMOS with FoM 157.4 fJ/conversion-step [15] have been demonstrated.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Passive Charge Sharing-Based Segmented SAR ADCs

Wang

Shi

2020

IEEE Trans. VLSI Syst.

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This article presents the theoretical analysis of passive charge sharing-based segmented successive-approximationregister (SAR) analog-to-digital converter (ADC), where the precise reference source in a capacitive digital-to-analog converter (CDAC) is replaced by a capacitor that is β times larger than its bit capacitor and precharged to the reference level, known as a reference charge reservoir (RCR). A segmented SAR-ADC uses a coarse SAR-ADC to compute some most significant bits (MSBs). Four methods, namely aligned switching (AS) with bitwise RCRs, AS with a subsample-wise RCR, detect-and-skip aligned switching (DAS-AS) with bitwise RCRs, and DAS-AS with a subsamplewise RCR are introduced for setting fine MSBs. Closed-form analytic expressions of the reference error due to the finite reference capacitance are derived and validated by behavioral modeling and circuit simulation of an 11-bit 50 MS/s segmented SAR ADC in 65-nm CMOS technology. The error expressions can be used to select one of the four methods for setting the fine MSBs and to determine β for the required linearity or for implementing digital circuitry for precise error correction.

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Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results

Cited by 28 publications

References 8 publications

Design of reduced-current overcurrent protection circuit based on GBDT model

Design of reduced-current overcurrent protection circuit based on GBDT model

A 0.002‐mm ² 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)

Analysis of Passive Charge Sharing-Based Segmented SAR ADCs

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Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results

Cited by 28 publications

References 8 publications

Design of reduced-current overcurrent protection circuit based on GBDT model

Design of reduced-current overcurrent protection circuit based on GBDT model

A 0.002‐mm 2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)

Analysis of Passive Charge Sharing-Based Segmented SAR ADCs

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Product

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A 0.002‐mm ² 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)