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This paper presents an extensive literature review on Binary Neural Network (BNN). BNN utilizes binary weights and activation function parameters to substitute the full-precision values. In digital implementations, BNN replaces the complex calculations of Convolutional Neural Networks (CNNs) with simple bitwise operations. BNN optimizes large computation and memory storage requirements, which leads to less area and power consumption compared to full-precision models. Although there are many advantages of BNN, the binarization process has a significant impact on the performance and accuracy of the generated models. To reflect the state-of-the-art in BNN and explore how to develop and improve BNNbased models, we conduct a systematic literature review on BNN with data extracted from 239 research studies. Our review discusses various BNN architectures and the optimization approaches developed to improve their performance. There are three main research directions in BNN: accuracy optimization, compression optimization, and acceleration optimization. The accuracy optimization approaches include quantization error reduction, special regularization, gradient error minimization, and network structure. The compression optimization approaches combine fractional BNN and pruning. The acceleration optimization approaches comprise computing in-memory, FPGA-based implementations, and ASIC-based implementations. At the end of our review, we present a comprehensive analysis of BNN applications and their evaluation metrics. Also, we shed some light on the most common BNN challenges and the future research trends of BNN.

Digital-to-analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital-to-time converter (DTC) and a time-to-voltage converter (TVC), is employed to form a low-power time-based DAC (T-DAC) that fits low-power low-speed applications. This novel conversion mixes the digital input code into a digital pulse width modulated (D-PWM) signal through the DTC circuit, then converts this D-PWM signal into an analogue voltage through the TVC circuit. This new T-DAC is not only an energy-efficient design but also an area-efficient implementation. Power optimization is achieved by controlling the supply voltage of the TVC circuit with a discontinuous waveform using a low bias current. Moreover, the implementation area is optimized by proposing a new DAC architecture with a coarse-fine DTC circuit. Post-layout simulations of the proposed T-DAC is conducted using industrial hardware-calibrated 0.13 μm. Complementary metal oxide semiconductor technology with a 1 V supply voltage, 1 MS/s conversion rate, and 0.9 μW power dissipation.

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