2015
DOI: 10.1039/c4tc01088d
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Precursor-based designs of nano-structures and their processing for Co(W) alloy films as a single layered barrier/liner layer in future Cu-interconnect

Abstract: We designed Co(W) films with the self-assembled grain-boundary stuffing as a single-layer barrier/liner for future ULSI Cu-interconnects. HR-TEM and EDX observations confirmed the validity of our materials design and good barrier performance in Co(W) films.

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Cited by 14 publications
(21 citation statements)
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“…Intermetallic phases in Pt–In, Pt–Sn, and Ni–Fe systems have been obtained by the postdeposition reduction of the corresponding ALD oxides. There are also some ALD studies on metal alloys, such as Pt–Ir, Pd–Pt, Ru–Pt, Ru–Co, Co–W, Co–Pt, Ru–Mn, and Cu–Mn, but no reports exist on materials exhibiting a specific intermetallic structure. Co–Sn and Ni–Sn with varying stoichiometry, including the intermetallic Co 3 Sn 2 and Ni 3 Sn 2 phases, have generally been prepared by, for example, ball milling, melting, different solution‐based techniques, solvo‐ and hydrothermal routes, electrodeposition, sputtering, and electron beam evaporation .…”
Section: Introductionmentioning
confidence: 99%
“…Intermetallic phases in Pt–In, Pt–Sn, and Ni–Fe systems have been obtained by the postdeposition reduction of the corresponding ALD oxides. There are also some ALD studies on metal alloys, such as Pt–Ir, Pd–Pt, Ru–Pt, Ru–Co, Co–W, Co–Pt, Ru–Mn, and Cu–Mn, but no reports exist on materials exhibiting a specific intermetallic structure. Co–Sn and Ni–Sn with varying stoichiometry, including the intermetallic Co 3 Sn 2 and Ni 3 Sn 2 phases, have generally been prepared by, for example, ball milling, melting, different solution‐based techniques, solvo‐ and hydrothermal routes, electrodeposition, sputtering, and electron beam evaporation .…”
Section: Introductionmentioning
confidence: 99%
“…With the development of integrated circuits of the higher density and speed, Cu is being used as a main metallic interconnect material because of its low resistance‐capacitance (RC) delay of integrated circuit (IC) and high electromigration resistance of metallic interconnect lines . As the feature size of electronic devices in IC technology is continuously scaling down gradually, the interdiffusion between materials become more severe at the same the temperatures of processing and operation.…”
Section: Introductionmentioning
confidence: 99%
“…Chipmakers are changing these barrier and liner layers 166 either by changing processes from physical vapor deposition (PVD) to atomic layer deposition (ALD) for better thickness control (as already implemented for the TaN barrier), or by changing materials (such as moving the liner from Ta to Co to Ru), or perhaps even by layer elimination (i.e. using a single alloy for the barrier and liner, or eliminating the Cu seed layer and plating directly onto the liner).…”
Section: Challenges In Scaling Interconnectsmentioning
confidence: 99%