Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization

Islam, Mahzabeen; Banerjee, Soumik; Meswani, Mitesh R.; Kavi, Krishna M.

doi:10.1145/2989081.2989129

Cited by 8 publications

(2 citation statements)

References 21 publications

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“…Planar moves the data access outside of the primary core, just as standard prefetching does. In contrast, it is driven by access code derived from the application and it also reduces data motion whereas prefetchers typically increase it [28]. Prefetchers for workloads most similar to those evaluated here include the works of Ainsworth et al [1], Kocberber et al [31] and Kumar et al [34] Unlike them, Planar is a general purpose approach suitable for multi-core scenarios.…”

Section: Related Workmentioning

confidence: 99%

Planar

Barredo

Armejach

Beard

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with multi-core systems, (ii) hides rearrangement latency, and (iii) provides the necessary interfaces to ease programmability.In this work we present Planar, a programmable near-memory accelerator that rearranges sparse data into dense. By placing Planar devices at the memory controller level we enable a design that scales well with multi-core systems, hides operation latency by performing non-blocking fine-grain data rearrangements, and eases programmability by supporting virtual memory and conventional memory allocation mechanisms. Our evaluation shows that Planar leads to significant reductions in data movement and dynamic energy, providing an average 4.58× speedup. CCS CONCEPTS• Hardware → Memory and dense storage; • Computer systems organization → Multicore architectures; • General and reference → Performance; • Computing methodologies → Vector / streaming algorithms.

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Section: Related Workmentioning

confidence: 99%

Planar

Barredo

Armejach

Beard

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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“…To overcome this pitfall, we suggest a prefetcher-based hybrid main memory, as shown in Figure 2b. With the prefetcher, the possibility of maintaining hot data in the DRAM increases, which may hide the long latency of the PCM [9]. Additionally, we adopt a small SRAM prefetch buffer to guarantee that the prefetching sequences do not disturb the requests from the processor.…”

Section: Motivations: Dram/pcm Hybrid Main Memory Systemmentioning

confidence: 99%

Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System

Kim

Yoon

2020

Electronics

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This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

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