Probabilistic dual-Vth leakage optimization under variability

Davoodi,; Srivastava, Ankur

doi:10.1109/lpe.2005.195504

Cited by 4 publications

(11 citation statements)

References 6 publications

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“…There are many existing literatures [2]- [10][12] on this topic, the basic idea is to find out gates which should be assigned high V th by queuing all the gates in certain order, and then to assign these gates high V th until the queue is empty. In this paper, a dual V th assignment scheme modified on our previous work [12] is used in the reduced DAG after our DAG pruning phase.…”

Section: Dual V Th Assignmentmentioning

confidence: 99%

“…As technology scaling, process variation can severely affect both power and timing yield. Hence, some researchers devoted themselves to probabilistic dual V th assignment approaches [8]- [10] which statistically optimized the leakage power and circuit performance. However, little work has been done to improve the speed of circuit optimization based on statistical timing analysis.…”

Section: Introductionmentioning

confidence: 99%

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LEAKAGE POWER REDUCTION THROUGH DUAL V_th ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

Wang

Shen

Luo

et al. 2009

J CIRCUIT SYST COMP

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†In today's sub-100nm CMOS technologies, leakage current has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits. Dual V th assignment, which is proven to be an effective method of reducing leakage power in the past, is also effective in today's technologies with certain modifications. In the paper, based on a statistical timing analysis (SSTA) framework we presented a dual V th assignment method which can effectively reduce the leakage power even in the presence of large V th variation. Besides, we use a statistical DAG pruning method which takes correlation between gates into account to speed up the dual V th assignment algorithm. Experimental results show that statistical dual V th assignment can reduce on average 40% more leakage current compared with conventional static method without affecting the performance constraints. Our DAG pruning method can reduce on average 30% gates in the circuit and save up to 50% of the total run time.

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Section: Dual V Th Assignmentmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

LEAKAGE POWER REDUCTION THROUGH DUAL V_th ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

Wang

Shen

Luo

et al. 2009

J CIRCUIT SYST COMP

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show abstract

“…At the same time, the increase in variability of several key process parameters can significantly affect the design and optimization of low power circuits in the nanometer regime [1][2][3]. Due to the exponential relation of leakage current with some process parameters, such as the effective gate length, oxide thickness and doping concentration, process variations can cause a significant increase in the leakage current.…”

Section: Introductionmentioning

confidence: 99%

“…Due to the exponential relation of leakage current with some process parameters, such as the effective gate length, oxide thickness and doping concentration, process variations can cause a significant increase in the leakage current. To minimize the effect of process variation, some techniques [1][2][3] statistically optimize the leakage power and circuit performance by dual-V th assignment. Leakage current and delay are treated as random variables.…”

Section: Introductionmentioning

confidence: 99%

“…Leakage current and delay are treated as random variables. A dynamic programming approach for leakage optimization by dual-V th assignment has been proposed [2] using two pruning criteria that stochastically identify pareto-optimal solutions and prune the sub-optimal ones. Another approach [1] solves the statistical leakage minimization problem by a theoretically rigorous formulation for dual-V th assignment and gate sizing.…”

Section: Introductionmentioning

confidence: 99%

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Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Agrawal

2008

21st International Conference on VLSI Design (VLSID 2008)

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Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path balancing) increases because glitches randomly start reappearing under the influence of process variation. Combining existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which combines glitch elimination and dual-threshold design to statistically minimize the total power in a glitch-free circuit under process variation.

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Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

Tao¹,

Dong²,

Wang³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Probabilistic dual-Vth leakage optimization under variability

Cited by 4 publications

References 6 publications

LEAKAGE POWER REDUCTION THROUGH DUAL V_th ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

LEAKAGE POWER REDUCTION THROUGH DUAL V_th ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

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Probabilistic dual-Vth leakage optimization under variability

Cited by 4 publications

References 6 publications

LEAKAGE POWER REDUCTION THROUGH DUAL Vth ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

LEAKAGE POWER REDUCTION THROUGH DUAL Vth ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

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Product

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LEAKAGE POWER REDUCTION THROUGH DUAL V_th ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

LEAKAGE POWER REDUCTION THROUGH DUAL V_th ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION