Procedure placement using temporal-ordering information

Abstract

Instruction cache performance is important to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate and the instruction working set size during execution. This means that the performance of an executable can be improved by applying a code-placement algorithm that minimizes instruction cache conflicts and improves spatial locality. We describe an algorithm for procedure placement, one type of code placement, that significantly differs from previous approaches in the type of information used to drive the placement algorithm. In particular, we gather temporal-ordering information that summarizes the interleaving of procedures in a program trace. Our algorithm uses this information along with cache configuration and procedure size information to better estimate the conflict cost of a potential procedure ordering. It optimizes the procedure placement for single level and multilevel caches. In addition to reducing instruction cache conflicts, the algorithm simultaneously minimizes the instruction working set size of the program. We compare the performance of our algorithm with a particularly successful procedure-placement algorithm and show noticeable improvements in the instruction cache behavior, while maintaining the same instruction working set size.

Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems

“…The goal of our work was to find a low-overhead technique to provide moderate improvement, not a high-overhead technique that provides the best possible improvement. Like Gloy, we also realized that even small changes can make a difference in performance [9].…”

“…This can be used as a compile time optimization to effectively reduce cache misses. Procedure placement using temporal ordering was improved upon by Gloy and Smith [3], using profile-driven code-placement with a weighted call graph to derive an improved procedure ordering.…”

HitME: Low power Hit MEmory buffer for embedded systems

“…Examples of these techniques include code compression to reduce the memory bus traffic [3][4] [5], efficient cache management strategies such as branch alignment [7] [8] and code placement [6] [9], scratchpad memories [10] and the addition of tiny memories on top of existing cache memories (loop cache [11] [12] and filter cache [13]). …”

Efficient and effective simulation of memory maps for system-on-chip

“…They differ based on: 1) the granularity assumed by the algorithm, and 2) the conflict model used to guide the memory placement. Some of them apply to code [7,10,4,8], while others to data [2,11,3]. In the past, the improvement of cache memory performance was the main issue [7,10,4,2], today we start to see that other kind of memories, such as DRAM, may have a significant role in the optimization of system performance as well [3].…”

“…For code placement, procedures and basic blocks are by far the most natural code boundaries which have been considered [7,4]; however, some results refer to more complex code structures such as basic block traces [10] or global control-flow graphs where the procedure boundaries are disregarded [8]. Global variables, arrays and local variables allocated in the program stack are instead the typical objects considered by data placement algorithms [2,11,3].…”