Process Complexity and Cost Considerations of Multi-Layer Die Stacks

Velenis, Dimitrios; Vos, Joeri De; Kim, Soon-Wook; Derakhshandeh, Jaber; Bex, Pieter; Capuz, Giovanni; Suhard, Samuel; Rebibis, Kenneth June; Huylenbroeck, Stefaan Van; Marinissen, Erik Jan; Phommahaxay, Alain; Miller, Andy; Beyer, Gerald; Plas, G. Van der; Beyne, Eric

doi:10.1109/3dic48104.2019.9058876

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Die Cost Scaling Scenarios1

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“…In case 2 instead, 3D memory-onlogic with wafer-to-wafer hybrid bonding (W2W) is considered. [5,6] In this case, the logic and memory die do not necessarily need to be the same technology node. Figure 6b shows an example of the relative wafer cost, considering a die from case 1 and two W2W bonded dies.…”

Section: Die Cost Scaling Scenariosmentioning

confidence: 99%

Investigation of die-cost scaling scenarios in future technologies

Mirabelli,

Tsai,

Chang

et al. 2024

DTCO and Computational Patterning III

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The concurrent saturation in dimensional scaling and increase in manufacturing cost and complexity has caused the overall semiconductor manufacturing cost to significantly increase. As a result, the cost per transistor is predicted to sharply increase in future technologies, deviating from the typical 30% cost per transistor reduction. This work explores the use of 3D-integration technologies, as wafer-to-wafer hybrid bonding, for both mobile and high-performance application. It is observed that the use of 3D-integration schemes, can reduce the overall die cost at same functionality, paving the way for cost-effective scaling solutions in future technologies.

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Section: Die Cost Scaling Scenariosmentioning

confidence: 99%