Process damages in HfO/sub 2/TiN stacks: the key role of H/sup 0/ and H/sub 2/ anneals

Garros, X.; Reimbold, G.; Louveau, O.; Holliger, P.; Hobbs, C.; Leroux, C.; Nguyen, L.; Martín, F.; Boulanger, F.

doi:10.1109/iedm.2005.1609303

Cited by 4 publications

(2 citation statements)

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“…In that case, large concentration of atomic hydrogen close to the Si interface may generate additional interface defects like in SiO2 oxides [18]. However plasma damages are strongly reduced when reducing stress voltage and may be acceptable for some applications [19]. The last part of this article deals with the Process Induced Damages PID which occur during the CMOS process.…”

Section: Passivation Of Interface States By N 2 /H 2 Anneals (Fga)mentioning

confidence: 99%

Interface States in Hf-Based Stacks and their Impact on the Reliability of these Alternative Oxides

Garros¹,

Reimbold²,

Martín³

et al. 2006

ECS Trans.

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This paper investigates interface states in Hf-based devices with metal gate. By electrical measurements we first show that the interface defects of HfO2 stacks are very similar to those of conventional SiO2 oxides. To passivate these defects forming gas anneals FGA under N2/H2 can be performed at high temperature T>500{degree sign}C in Hf-based oxide. We also propose for the first time the use of an atomic H0 plasma performed at low temperature T~300{degree sign}C to passivate these interface defects. Finally we investigate the impact of the interface states on the reliability of High-K dielectrics. The interface state generation in HfO2 oxides annealed by FGA is similar to the one induced by NBTI stress in SiO2. On the other hand, in H0 annealed samples, degradation is enhanced due to plasma charging in the oxide. But some of the interface degradations induced by PID can be cured by standard thermal treatments.

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Section: Passivation Of Interface States By N 2 /H 2 Anneals (Fga)mentioning

confidence: 99%

Interface States in Hf-Based Stacks and their Impact on the Reliability of these Alternative Oxides

Garros¹,

Reimbold²,

Martín³

et al. 2006

ECS Trans.

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“…Plasma-Induced Damage (PID) has been an important concern for equipment vendors and fabs in both traditional SiO2 based and advanced high-k dielectric based processes [1][2][3][4][5][6]. Fig.…”

Section: Introductionmentioning

confidence: 99%

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage

Choi

Satapathy

Keane

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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We propose a test circuit for characterizing PlasmaInduced Damage (PID) based on a ring oscillator array for collecting high-quality BTI statistics. Two types of ring oscillators, PID protected and PID damaged, with built-in antenna structures were designed to separate PID from other effects. A beat frequency (BF) detection scheme was adopted to achieve high frequency measurement precision (>0.01%) in a short measurement time (>1μs) to prevent unwanted BTI recovery. The proposed circuit enables accurate PID-induced BTI lifetime prediction with different Antenna Ratios (ARs) in any type of device with any topology of antenna structure under any fabrication process. Measured frequency statistics from a 65nm test chip shows a 1.15% shift in the average frequency as a result of PID.

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On the Recovery of Simulated Plasma Process Induced Damage in High-&#954; Dielectrics

Pantisano

O’Sullivan

Roussel

et al. 2006

2006 IEEE International Conference on IC Design and Technology

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A detailed analysis of the ability of high-K materials to recover HfO2 and HfSiON films in both cases, where the effects of P2IID from plasma damage, as simulated by Fowler-Nordheim stress is on defect creation are examined utilising several techniques, presented. Forming gas and high temperature rapid thermal anneal namely, charge (/time) to breakdown, stress induced leakage (RTA) steps are compared to determine their efficiency at trap currents and charge pumping. The recovery of these P2IID defects recovery. The annealing responses of the technologically relevant through several annealing steps is also examined in detail. HfSiON and HfO2 materials (EOT<2nm) are correlated with EXPERIMENTAL structural differences in these dielectrics, as well as the trap generation rate, centroids and defect de-passivation. We show that Conventional MOS capacitors and FET's with encapsulated TaN plasma damage can be successfully recovered for HfO2 by high gates were utilised. A 1 nm chemical oxide was used as the temperature annealing. starting surface. ALD HfO2 or MOCVD HfSiO(N) (2 nm 45/55 Si/Hf nMOS, and 3 nm 30/70 pMOS) were deposited. An 800°C

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Process damages in HfO/sub 2/TiN stacks: the key role of H/sup 0/ and H/sub 2/ anneals

Cited by 4 publications

References 4 publications

Interface States in Hf-Based Stacks and their Impact on the Reliability of these Alternative Oxides

Interface States in Hf-Based Stacks and their Impact on the Reliability of these Alternative Oxides

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage

On the Recovery of Simulated Plasma Process Induced Damage in High-&#954; Dielectrics

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Process damages in HfO/sub 2/TiN stacks: the key role of H/sup 0/ and H/sub 2/ anneals

Cited by 4 publications

References 4 publications

Interface States in Hf-Based Stacks and their Impact on the Reliability of these Alternative Oxides

Interface States in Hf-Based Stacks and their Impact on the Reliability of these Alternative Oxides

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage

On the Recovery of Simulated Plasma Process Induced Damage in High-&amp;#954; Dielectrics

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On the Recovery of Simulated Plasma Process Induced Damage in High-κ Dielectrics