Process-induced bias: a study of resist design, device node, illumination conditions, and process implications

As die feature sizes continue to decrease, advanced process control has become essential for controlling profile and CD uniformity across the wafer. Gate CD variation must be suppressed by process optimization of lithography, photoresist trim, and gate etch in order to achieve the demanding CD control tolerances. Currently, APC is used in the lithography and etch processes for within wafer (WiW) and wafer-to-wafer (W2W) CD control. APC can make improvements in process results, but there is still variation that needs to be further reduced. Analysis of the current lithography edge CD showed that the variation trend transferred to the post-etch edge CD measurement. Additionally, the etch process created variation in the edge CD independently of the lithography process. It can be challenging to compensate for the variations in the etch process and such compensations degrade through pitch OPC. Multivariable control of the etch process can reduce the need for compensations and, consequently, through pitch variation. A DOE was designed and run using the production etch process as a center reference for the creation of a WiW etch control model. This control model was then tested with a MATLAB based simulation program that simulates the etch production process sequence and the ability to target the edge CD. This demonstration shows that through rigorous methodology a multivariate model can be created for targeting both center CD (W2W) and edge CD (WiW) control, providing an opportunity at etch to reduce compensation for the etch variations at litho, and to provide the capability at etch to compensate for both litho and etch uniformity changes by wafer.

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“…The resulting impact is of this deviation is the degradation of the performance of OPC [11]. Figure 9.…”

Section: Constrained Regionmentioning

confidence: 97%

Increased uniformity control in a 45nm polysilicon gate etch process

Parkinson

Prager

Funk

et al. 2009

Metrology, Inspection, and Process Control for Microlithography XXIII

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“…[5][6][7] Process Improvement Potential -Line In the case of the space for LELE (Figure 14), the best performance would require not only hot plate zone compensation but also improvements in overlay. Overlay performance is based on the best results currently seen by IMEC.…”

Section: Overall Comparison and Potential Improvementmentioning

confidence: 98%

A CDU comparison of double patterning process options using Monte Carlo simulation

et al. 2009

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Determination of the optimal double patterning scheme depends on cost, integration complexity, and performance. This paper will compare the overall CDU performance of litho-etch-litho-etch (LELE) versus a spacer approach. The authors use Monte Carlo simulation as a way to rigorously account for the effect of each contributor to the overall CD variation of the double patterning process. Monte Carlo simulation has been applied to determine CD variations in previous studies 1-2 , but this paper will extend the methodology into double patterning using a calibrated resist model with topography.

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Process-induced bias: a study of resist design, device node, illumination conditions, and process implications

Cited by 2 publications

References 1 publication

Increased uniformity control in a 45nm polysilicon gate etch process

Increased uniformity control in a 45nm polysilicon gate etch process

A CDU comparison of double patterning process options using Monte Carlo simulation

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