Process integration of double level copper-low k (k=2.8) interconnect

Carbon-doped SiO2 low k thin films were prepared by radio frequency plasma-enhanced chemical vapor deposition at 400°C from polymerization of tetramethylsilane (4MS) and copolymerization of tetramethylsilane and silane false(SiH4false) precursor, with nitrous oxide as the oxidant gas. Copolymer thin films from 4MS and SiH4 precursor show much higher deposition rates than polymer thin films from 4MS, if all other parameters are kept the same. The addition of SiH4 can significantly promote the plasma polymerization of 4MS. The structure and composition of these films were characterized using Fourier transform infrared and X-ray photoelectron spectroscopy. The physical properties of the films have been investigated by dielectric constant, refractive index, and thermal stability measurements. The two kinds of films have similar chemical composition and structure. The film as prepared shows excellent thermal stability at temperatures as high as 400°C and a dielectric constant of about 3, which indicates that it has potential as a low k dielectric for advanced interconnect applications. © 2001 The Electrochemical Society. All rights reserved.

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confidence: 99%

Characterization of Carbon-Doped SiO[sub 2] Low k Thin Films: Preparation by Plasma-Enhanced Chemical Vapor Deposition from Tetramethylsilane

Han

Pan

Chen

et al. 2001

“…1,2 Although either the trench or the via can be etched first in dual damascene etch process, most semiconductor manufacturers have chosen to adopt the via-first approach. 3,4 The via-first dual damascene etch process is shown in Fig. 1.…”

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confidence: 99%

Profile Evolution Simulation of Oxide Fencing during Via-First Dual Damascene Etching Processes

Jin

Sawin

2003

The introduction of copper interconnects has increased the use of dual damascene etching processes, which leads to new challenges for feature profile control. Oxide fencing around vias during the trench etch of the via-first dual damascene scheme can be detrimental to the device performance and therefore need to be eliminated. A systematic study of oxide fencing formation during via-first dual damascene etching processes is presented. A Monte Carlo technique associated with surface kinetics and cell removal algorithm is used to simulate the profile evolution, and the simulation results qualitatively agree with the experimental results taken from literature. The simulation indicated that the feature profile evolution is controlled by both the ion and neutral flux distribution along the etching surface and angular dependent etching yield. The shape of via, the SiO 2 :BARC etching selectivity, and etching chemistry can affect the oxide fencing. Bowed via can eliminate the oxide fencing, and tapered via will result in severe oxide fencing. Reducing etching selectivity can also control the height of oxide fencing, but it does not seem to be a practical solution. Less polymerizing chemistry causes much less severe oxide fencing than does more polymerizing chemistry. The simulation can thus serve as a useful guide for searching optimal profile evolution control conditions.

“…2 Low-k (k Ͻ 3.0) dielectrics are currently being extensively developed on both organic ͑carbon-based͒ and inorganic (SiO 2 -based͒ materials using both spin-on ͑SO͒ and chemical vapor deposition ͑CVD͒ techniques. [1][2][3][4][5][6][7][8][9][10] Although spin-on is the most widely used method, low-k films grown by CVD are recently receiving widespread attention for potential back-end-of-line applications. Remarkably, CVD techniques offer several key advantages, such as superior gap-filling capability and extremely uniform coating of large areas, which is crucial to future 300 mm wafers.…”

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confidence: 99%

Physical and Electrical Characteristics of F- and C-Doped Low Dielectric Constant Chemical Vapor Deposited Oxides

Shiung

Chiang

et al. 2001

This work compares the physical and electrical properties of two species of inorganic low dielectric constant ͑low-k͒ chemical vapor deposited ͑CVD͒ oxides, F-doped fluorinated silicate glass ͑FSG, k ϭ 3.5͒ and C-doped organosilicate glass ͑OSG, k ϭ 2.9). Experimental results indicate that FSG has a higher thermal stability ͑Ͼ600°C͒ than OSG ͑500°C͒, based on the results of thermal annealing for 30 min in an N 2 ambient. The degradation of the low-k property in OSG is mainly due to the thermal decomposition of methyl (ϪCH 3 ) groups at temperatures above 500°C. For the Cu gated oxide-sandwiched low-k dielectric metal-insulator-semiconductor ͑MIS͒ capacitors, Cu penetration was observed in both FSG and OSG after the MIS capacitors were bias-temperature stressed at 250 and 150°C, respectively, with an effective applied field of 0.8 MV/cm. Specifically, Cu appeared to drift more readily in OSG than in FSG, presumably because OSG has a more porous and less dense structure than FSG. The Cu permeation can be impeded by a thin nitride ͑SiN͒ barrier layer.