Process Optimization of Radiation-Hardened CMOS Integrated Circuits

Correlation between preirradiation 1/f noise and postirradiation oxide-trapped charge in MOS transistors

“…Values of AVot and AV;., are uncertain by the larger of f 3 0 mV and f5%. As expected, devices with thinner oxides showed relatively smaller AV,, and Al& than devices with thicker oxides (e.g., compare wafers 22, 32, and 44) [23,24], and devices without high-temperature anneals showed less AV,, than devices with high-temperature anneals [21,23,25]. Note that the differences in AV;., with these process changes are smaller and less systematic than the differences in AVot [21].…”

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

“…The obtained DN ft values are so high comparing to the positive gate bias regime, and DN ft is approximately only 50% less than in the case of positive HEFS. In the case of IR, this difference is significantly higher, and the DN ft for the positive IR is more than five times higher than for the negative IR [48,49]. This so large difference in DN ft for IR is reasonable since it could be assumed that the FT are located near oxide/Si interface for positive gate bias (Fig.…”

Total ionizing dose response of fluorine implanted Silicon-On-Insulator buried oxide

“…The experimental procedure adopted to fabricate the capacitors has implemented techniques which have previously been shown to improve the radiation tolerance, as described by Aubuchon [18], Derbenwick [12], Naruke [13] and more recently Fleetwood [19]. The adopted techniques were (a) to use h1 0 0i silicon wafers which minimise the number of dangling bonds and therefore interface traps at the Si-SiO 2 interface, (b) select the optimum silicon dioxide growth temperature of 850°C for wet thermally grown oxide, (c) limit the post oxidation anneal temperature to 850°C to minimise post irradiation oxide degradation and, (d) deposit the aluminium contacts via thermal evaporation.…”

“…The BOX capacitors were fabricated using commercial smart-cut Ò wafers, which had the top silicon layer over etched by 5% using Reactive Ion Etching (RIE) to reveal the 400 nm BOX. The thermal oxide capacitors were fabricated using a wet thermal oxide grown at a temperature of 850°C [12,13] for 9.5 h to achieve a target oxide thickness of 400 nm. From ellipsometer measurements, the wafer oxide thicknesses were 423 ± 10 nm and 390 ± 10 nm for the thermal oxide and BOX capacitors, respectively.…”