Process techniques of charge transfer time reduction for high speed CMOS image sensors

Abstract

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 64 pixels was designed and implemented in the 0.18 m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 s is achieved and 31% of image lag was reduced by using the proposed process techniques.

Mitigating charge spill-back induced image lag with a multi-level transfer gate pulse in PPD image sensors

“…There are several factors which can influence lag, such as the pixel size and shape 1 , transfer gate voltage 2 , FD reset voltage 3 and signal level 4 . Many novel designs in pixel architecture have sought to reduce the effects of lag [5][6][7] , with varying degrees of success. Image lag is more prominent in large pixels with high full well capacity, which tend to dominate high-performance scientific applications.…”