Process variation aware thread mapping for Chip Multiprocessors

Abstract

Abstract-With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identicallydesigned processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.

An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms

“…In [6] the main purpose is to maximize performance only. Energy minimization is not considered also in [12,15].…”

“…Previous researches demonstrate that, by adjusting workload allocation, it is possible to compensate these effects [6,[10][11][12][13]15]. In this context, variation-aware task allocation consists Research activity supported by the European project REALITY FP7-2008-IST-1-216537 and MODERN ENIAC 2008-1 contract n. 21000 in finding the best allocation to minimizes a given target objective in presence of speed and power consumption variations.…”

On-Chip Dynamic Resource Management

“…It is to be noted that application mapping policies are largely targeted at applications that are task graph and message passing based, exhibiting higher degree of task level parallelism and concurrency. Further, adaptive mapping policies have considered factors such as process variation (Hong et al, 2009). A summary of application mapping as per their core selection criteria is presented in Table 3.1.…”

Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints

“…Moreover, the approaches are fully static and cannot be applied on-line. A process variationaware thread mapping has been recently proposed in [6]. In this work, the main purpose is to maximize performance and focuses on loop-intensive application.…”