Processes for multilevel metallization

Abstract

Film deposition and etching techniques for producing multilevel metallized structures on complex devices are reviewed. Emphasis is placed on process procedures for controlled contouring of topographic features induced during pattern etching, techniques for ensuring coverage by deposited films of topography introduced into the substrate, and dielectric deposition procedures that enhance breakdown strength and minimize pinholes. Broadly, the classes of processes discussed are the following: (i) metallization techniques that reduce susceptibility to electromigration and hillock formation and that ensure step coverage; (ii) dielectric deposition techniques that result in good step coverage, low stress, and low pinhole density; (iii) photolithographic and etching techniques that can taper steps generated in the films and that do not form pinholes.

Reactive Ion Etching

“…Materials that have been used for this purpose include thick films of plasma-deposited nitrides and oxide, spun-on glass (SOG), organic photoresists, polyimides, and flowed phospho rus-doped silicon oxide (P glass) [117,118]. Planarization of topographical features, particularly those of silicon oxide over polysilicon or other materials, is desirable in order to improve opportu nities for high-resolution lithography as well as for more uniform step coverage by interconnect metallizations.…”

Effect of substrate on the step coverage of plasma-enhanced chemical-vapor deposited tetraethylorthosilicate films

“…1 The step coverage has been previously reported to depend on deposition parameters, including deposition temperature, total gas flow, and substrate material. [1][2][3][4][5][6][7] Low pressure CVD ͑LPCVD͒ yields better step coverage than PECVD and PECVD provides better step coverage than atmospheric pressure CVD ͑APCVD͒. 4,5 The application of plasma deposition in the microelectronics industry began in 1963.…”

Doping of copper indium selenide (CuInSe2) crystals: evidence for influence of thermal defects

“…One fact that is uncontested, however, is that high Se pressure dopes CuInSe2 samples p-type at elevated temperatures. Parkes et al 7 found that a 15-min anneal at 600 °C under an excess of Se pressure (>3 X 104 Pa) was sufficient to type convert an n-type sample to p-type.…”