Processing by Data and Program Blocks

Schaffner,

doi:10.1109/tc.1978.1674991

Cited by 4 publications

(1 citation statement)

References 8 publications

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“…Due to a lack of enabling technology, the reconfiguration was done manually. Mario Schaffner's Circulating Page Structure (CPS) machine [23] implemented a form of hardware paging scheme where the application task was partitioned into pages which circulate through the programmable hardware to compute the task.…”

Section: Previous Workmentioning

confidence: 99%

Compiler Optimizations for Adaptive EPIC Processors

2001

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Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new instructions. Configuration selection is the problem of narrowing down the choices of which synthesized instruction (from the set generated by the instruction synthesis phase) to use for each of the code regions that will be mapped to programmable logic. Unlike traditional optimizing compilers, the adaptive EPIC compiler must deal with the existence of synthesized instructions. Compilation techniques addressing each of these problems will be presented.

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Section: Previous Workmentioning

confidence: 99%

Compiler Optimizations for Adaptive EPIC Processors

2001

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A Multiprocessor-System for the Acquisition and Analysis of Video Image Sequences

Brennecke

Hahne

Heintzen

1980

Informatik-Fachberichte

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High speed intelligent machine through programmable hardware: application to genomic systems

Lemoine¹,

Maillet-Contoz²,

Merceron³

et al.

Proceedings of 1st International Conference on Conventional and Knowledge Based Intelligent Electronic Systems. KES '97

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This paper proposes a new technology for intelligent machines, based on the concept of programmable hardware. To build an intelligent system, the designer has to adapt it t o the problem. First we show that programmable hardware is an intermediate step for building configurations, in order to choose the best architecture. In this case, the tasks are performed in a time period that respects human cognitive capacities. Next is detailed a multilevel model composed of the cognitive, software and hardware levels. An experimental platform has been built based on programmable hardware, and used in a "Grand Challenge" problem: knowledge discovery in genetic sequence databases, to compare the relative efficiencies of programmable hardware and classical Von Neumann based architecture. Programmable hardware has shown to have a significantly faster response time, which is essential for modern day intelligent machine user interaction.

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Processing by Data and Program Blocks

Cited by 4 publications

References 8 publications

Compiler Optimizations for Adaptive EPIC Processors

Compiler Optimizations for Adaptive EPIC Processors

A Multiprocessor-System for the Acquisition and Analysis of Video Image Sequences

High speed intelligent machine through programmable hardware: application to genomic systems

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