Processor- and memory-based checkpoint and rollback recovery

Bowen, N.S.; Pradham, D.K.

doi:10.1109/2.191981

Cited by 59 publications

(19 citation statements)

References 16 publications

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“…Horst et al (1993) presented a model to evaluate vulnerability of the systems built around micro-processors in case of undetected data corruptions due to transient faults. Bowen and Pradhan (1993) suggested some solution of recovery of such systems. Since most of the systems are designed using commercial off-the-shelf (COTS) components, assurance of reliable working of such a system has remained a big challenge to the designers.…”

Section: Errors Versus Techniquesmentioning

confidence: 98%

A survey of memory error correcting techniques for improved reliability

Mukati

2011

Journal of Network and Computer Applications

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Section: Errors Versus Techniquesmentioning

confidence: 98%

A survey of memory error correcting techniques for improved reliability

Mukati

2011

Journal of Network and Computer Applications

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“…SRTR (Simultaneously and Redundantly Threaded processors with Recovery) [5] extends SRT by adding recovery support. In dual-processor devices which indicate both a dual-core CMP chip and different dies, the lockstep techniques have been used for fault detection [6][7][8].…”

Section: Related Workmentioning

confidence: 99%

Pair and swap: An approach to graceful degradation for dependable chip multiprocessors

Imai

Nagai

Nanya

2010

2010 International Conference on Dependable Systems and Networks Workshops (DSN-W)

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In this paper, we propose a processor-level fault tolerance technique called "Pair and Swap (P&S)" for a multicore chip. In the P&S system, a 2n-cores-CMP (Chip Multiprocessor) which contains 2n processor cores composes n pairs. Two identical copies of a given task are executed on each pair of two processor cores and the results are compared repeatedly. If a fault is detected by a mismatch, partners of the mismatched pair are swapped with another pair and the mismatched task is re-executed from the latest checkpoint. Then, it is decided whether the fault is transient or permanent. If it is permanent, the faulty core is identified and isolated to reconfigure the entire system. P&S enables graceful degradation and tolerates both permanent and transient faults. We evaluate the performance of the proposed P&S and traditional triple module redundancy (TMR) using the Markov chains. The mean computation to failure of the P&S is about 1.4 times larger than that of dynamic TMR scheme.

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“…Rollback recovery has been widely used for large block sizes with coarse-grained recovery, typically at the processor level [23][24][25]. In this section we design a fine-grained rollback technique that can tolerate higher fault rates than previous rollback techniques and achieve high system reliability.…”

Section: Design Structurementioning

confidence: 99%

Fault-tolerant sub-lithographic design with rollback recovery

Naeimi

DeHon

2008

Nanotechnology

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Shrinking feature sizes and energy levels coupled with high clock rates and decreasing node capacitance lead us into a regime where transient errors in logic cannot be ignored. Consequently, several recent studies have focused on feed-forward spatial redundancy techniques to combat these high transient fault rates. To complement these studies, we analyze fine-grained rollback techniques and show that they can offer lower spatial redundancy factors with no significant impact on system performance for fault rates up to one fault per device per ten million cycles of operation (P f = 10 −7 ) in systems with 10 12 susceptible devices. Further, we concretely demonstrate these claims on nanowire-based programmable logic arrays. Despite expensive rollback buffers and general-purpose, conservative analysis, we show the area overhead factor of our technique is roughly an order of magnitude lower than a gate level feed-forward redundancy scheme.

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Processor- and memory-based checkpoint and rollback recovery

Cited by 59 publications

References 16 publications

A survey of memory error correcting techniques for improved reliability

A survey of memory error correcting techniques for improved reliability

Pair and swap: An approach to graceful degradation for dependable chip multiprocessors

Fault-tolerant sub-lithographic design with rollback recovery

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