Profiling and mapping of parallel workloads on network processors

Weng, Ning; Wolf, Tilman

doi:10.1145/1066677.1066879

Cited by 23 publications

(25 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [14], the authors use an annotated directed acyclic graph (ADAG) to generate a group of pipelined tasks by the dynamic profiling and instruction tracing method. While in this paper profiling, grouping, and allocating tasks are carried out manually considering the overall performance of the NePA system and the workload which is scheduled to PEs.…”

Section: Methodology Of Parallel and Pipeline Processing For Block CImentioning

confidence: 99%

“…The authors of [8] have suggested maximizing the throughput of a pipelined multiprocessor system by effective assignment of flow tasks to pipeline stages on an NP platform. In the paper [14], they have introduced a methodology for profiling and scheduling networking workloads and applications on a highly parallel network processor architecture.…”

Section: Related Workmentioning

confidence: 99%

“…In their papers [16], [9], [8], [14], they have shown various parallel and pipeline task scheduling and mapping methodologies for block cipher algorithms. The proposed parallel and pipeline NoC implementation for block ciphers have been developed on their platforms.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

Yang

Bahn

Lee

et al. 2009

2009 Sixth International Conference on Information Technology: New Generations

View full text Add to dashboard Cite

The computational performance of Network-on-Chip (NoC) and Multi-Processor System-on-Chip (MPSoC) for implementing cryptographic block ciphers can be improved by exploiting parallel and pipeline execution. In this paper, we present a parallel and pipeline processing method for block cipher algorithms: Data Encryption Standard (DES), Triple-DES Algorithm (TDEA), and Advanced Encryption Standard (AES) based on pure software implementation on an NoC. The algorithms are decomposed into task loops, functions, and data flow for parallel and pipeline execution. The tasks are allocated by the proposed mapping strategy to each Processing Element (PE) which consists of a 32-bit Reduced Instruction Set Computer (RISC) core, internal memory, router, and Network Interface (NI) to communicate between PEs.The proposed approach is simulated by using Networked Processor Array (NePA), the cycle-accurate SystemC and Hardware Description Language (HDL) model platform. We show that our method has the advantage of flexibility as compared to previous implementations of cryptographic algorithms based on hardware and software co-design or traditional hardwired ASIC design. In addition, the simulation result presents that the parallel and pipeline processing approach for software block ciphers can be implemented on various NoC platforms which have different complexities and constraints.

show abstract

Section: Methodology Of Parallel and Pipeline Processing For Block CImentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

Yang

Bahn

Lee

et al. 2009

2009 Sixth International Conference on Information Technology: New Generations

View full text Add to dashboard Cite

show abstract

“…Ramaswamy et al [19] and Weng et al [20] presented randomization algorithms for task allocation on network processors with an objective of minimizing latency (not throughput) without considering multi-threading or process transformations. Ramamurthi et al [21] presented heuristic techniques for mapping applications to block multi-threaded multiprocessor architectures.…”

Section: Previous Workmentioning

confidence: 99%

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

Ostler

Chatha

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…The basic idea of randomized mapping is to randomly choose a valid mapping and evaluate its performance and repeat this process certain times. [7] and [8] present randomized mapping algorithms with different models for performance evaluation. Genetic algorithm maintains a population of candidate solutions that evolves over time and ultimately converges.…”

Section: Related Workmentioning

confidence: 99%

Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors

Yang

Zhang

et al.

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on-Chip. This paper proposes a novel scheduling algorithm, called Replication-based Partial Dynamic Scheduling (RPDS). It aims to improve the NP performance by combining the strategies of partial dynamic mapping and task replication with a 2-phase scheduling. RPDS differs from existing solutions in several aspects, e.g., the processing elements are heterogeneous, fully-connected, and multi-threading, the application is decomposed into directed acyclic graph tasks with continuous data-packets, and scheduling is conducted at both of initialization and run-time. Experimental results showed our algorithm could increase the largest average throughput by about 30% than those without dynamic phase replication.

show abstract

Profiling and mapping of parallel workloads on network processors

Cited by 23 publications

References 9 publications

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors

Contact Info

Product

Resources

About