Profiling tools for hardware/software partitioning of embedded applications

Suresh, Dinesh C.; Najjar, Walid; Vahid, Frank; Villarreal, Jason; Stitt, Greg

doi:10.1145/780757.780759

Cited by 8 publications

(9 citation statements)

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“…Media processing program execution tends to spend most of the time in frequent loop nests. By their very nature, MPSoC applications tend to follow the rule even more so than desktop type of application [22]. In this paper, the proposed approach focuses critical loops, those loop nests which appear frequently and consume much time every execution.…”

Section: A Application Modelmentioning

confidence: 99%

Parallel Processing of Sequential Media Algorithms on Heterogeneous Multi-Processor System-on-Chip

Zhao¹,

Wang²,

Yan³

et al. 2009

JCP

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Heterogeneous Multi-Processor System-on-Chip (MPSoC) and media processing are comprehensively applied in mobile electronic commerce. And heterogeneous MPSoCs provides more opportunities for parallelization accelerating of sequential media algorithms. However, the parallelization researches of heterogeneous MPSoC applications lags far behind the development of MPSoC hardware platform. Therefore, utilizing parallelization opportunity of MPSoC for improving performance and efficiency of media applications has been one of the hottest researches in the field of embedded system. This paper proposes a new approach that parallelizes sequential media algorithms on heterogeneous MPSoC using program transformation and application-to-architecture mapping techniques. Data locality and communication cost are optimized during the parallel processing. Moreover, the difference between processing elements, reflected in architecture templates, is used to achieve “the maximum” performance and efficiency of heterogeneous MPSoCs. Finally, an experiment shows the proposed approach can obtain approximate or better accelerating than the manual parallel processing by experienced designers.

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Section: A Application Modelmentioning

confidence: 99%

Parallel Processing of Sequential Media Algorithms on Heterogeneous Multi-Processor System-on-Chip

Zhao¹,

Wang²,

Yan³

et al. 2009

JCP

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“…For profiling the face detection algorithm, whose software implementation is in C, the FLAT profiler was used. The FLAT profiler provides loop/function level profile information (Suresh et al, 2003). The FLAT profiler identifies the mask correlation module (see Table 1) as the candidate core -a core is defined in this context as the set of all loops whose execution cost is higher than a threshold value -for optimisation.…”

Section: Profilingmentioning

confidence: 99%

An architectural level design methodology for smart camera applications

Saha

Kianzad

Schlessman

et al. 2009

IJES

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Today's embedded computing applications are characterised by increased functionality, and hence increased design complexity and processing requirements. The resulting design spaces are vast and designers are typically able to evaluate only small subsets of solutions due to lack of efficient design tools. In this paper, we propose an architectural level design methodology that provides a means for a comprehensive design space exploration for smart camera applications and enable designers to select higher quality solutions and provides substantial savings on the overall cost of the system. We present efficient, accurate and intuitive models for performance estimation and validate them with experiments.

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“…SpixTool [8] for SPARC or VTune [9] for Intel architectures, cf. [10] for an overview). Other tools, such as LISATek [11] include retargetable assembly-level profilers, based on an ADL model of the target machine.…”

mentioning

confidence: 99%

Fine-grained application source code profiling for ASIP design

Karuri¹,

Faruque²,

Kraemer³

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

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Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Languages (ADLs) and retargetable software development tools. However, for improved design efficiency, additional pre-architecture exploration tools are required to help narrow-down the huge design space and making coarsegrained Instruction Set Architecture (ISA) decisions before detailed ADL modeling. Extensive application code profiling is the key in such early design stages. Based on a novel code instrumentation technology, we present a microprofiling approach that fills the current gap between sourcelevel and instruction-level profilers and combines their advantages w.r.t. speed and accuracy. We show how the microprofiler is embedded into an advanced ASIP design flow and justify its use in a case study to design an MP3 decoder ASIP.

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Profiling tools for hardware/software partitioning of embedded applications

Abstract: ABSTRACT

Cited by 8 publications

References 0 publications

Parallel Processing of Sequential Media Algorithms on Heterogeneous Multi-Processor System-on-Chip

Parallel Processing of Sequential Media Algorithms on Heterogeneous Multi-Processor System-on-Chip

An architectural level design methodology for smart camera applications

Fine-grained application source code profiling for ASIP design

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