Programmable 2D linear filter for video applications

Hofer, Ron; Kamp, W.; Kunemund, R.; Soldner, H.

doi:10.1109/4.102668

Cited by 25 publications

(4 citation statements)

References 4 publications

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“…In image convolution for instance, line buffers which hold entire image columns are often needed in order to supply each input image pixel only once to the FPGA [19], [20]. A buffer element is a memory block with three parameters: overall size (in bits of memory), height and width.…”

Section: Floating Ports and Dynamic Blocksmentioning

confidence: 99%

From application descriptions to hardware in seconds: a logic-based approach to bridging the gap

Benkrid

Crookes

2004

IEEE Trans. VLSI Syst.

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This paper presents a high-level hardware description environment developed at Queen's University, Belfast, U.K., which aims to bridge the gap between application design and hardware description. The environment, called application-to-hardware (A2H), allows for efficient compilation of high-level application descriptions to field programmable gate array (FPGA) hardware in the form of EDIF netlist in seconds.A key concept in bridging the gap while retaining the hardware efficiency, is that of hardware skeletons. A hardware skeleton is a parameterized description of a task-specific architecture, to which the user can supply not only value parameters but also functions or even other skeletons. A skeleton contains built-in rules, which capture optimizations specific to the target hardware at the implementation phase. The rule-based logic programming language Prolog has been chosen as the base notation for the A2H environment. This paper includes descriptions of hardware skeletons abstractions in the particular context of image processing applications. The current implementation of our system targets Xilinx XC4000 and Virtex series FPGAs.Index Terms-Design automation, hardware skeletons, image and video processing, logic programming, reconfigurable systems, Xilinx FPGAs.

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Section: Floating Ports and Dynamic Blocksmentioning

confidence: 99%

From application descriptions to hardware in seconds: a logic-based approach to bridging the gap

Benkrid

Crookes

2004

IEEE Trans. VLSI Syst.

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“…Additionally, in many applications two or more convolutions with different coefficient masks have to be applied in parallel to the same video signal, e.g., for edge detection and pattern recognition. Several implementations of the 2D convolution algorithm for real time image processing are available [2], [3] or have been designed as prototypes [4]. The L64240 Multi-bit Filter from LSI-Logic [2] is a convolution chip for 8" 8 filter-taps, which is available for up to 20 MHz pel-frequency.…”

Section: Two-dimensional Convolutionmentioning

confidence: 99%

“…The Plessey PDSP16488 [3] is a one chip convolver, which operates at 10 MHz pel-frequency using 8 • 8 filter-taps and contains on-chip line delays of 512 pels per line. The convolver of Siemens [4] offers 7" 7 taps only for vertically symmetric coefficient masks, operates at 20 MHz pelfrequency and also contains internal line delays of up to 512 pels per line.…”

Section: Two-dimensional Convolutionmentioning

confidence: 99%

A defect-tolerant systolic array implementation for real time image processing

Ronner¹,

Pirsch²

1993

J VLSI Sign Process Syst Sign Image Video Technol

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An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved.The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester.The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders.High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.

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“…The other two special types of notch biquadratic filter are LPN and HPN biquadratic filters [47], [48], [49]. Active biquadratic filters can find many applications in sensor, biomedical, video, and audio crossover network applications [50], [51], [52], [53], [54], [55], [56]. For example, a two-way network divides the bass and high frequency ranges between two speakers [57], while a threeway network divides the bass, midrange and high frequency ranges between three speakers [58], thus requiring the design and implementation of electronically adjustable LP, HP, and BP filters from the same configuration.…”

Section: Introductionmentioning

confidence: 99%

Two New and Improved Electronically Adjustable Voltage-Mode Multifunction Biquadratic Filters With Independent Control of Band-Pass, High-Pass, and Low-Pass/Regular Notch Filter Gains

et al. 2023

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In this study, two new and improved electronically adjustable voltage-mode (VM) biquadratic filters using three off-the-shelf LT1228 integrated circuits (ICs), two grounded capacitors (GCs), and six resistors are proposed for independent control of the band-pass (BP), high-pass (HP), and low-pass/regular notch (LPN/RN) filter gains. Each proposed electronically adjustable VM multifunction biquadratic filter has one input and six output voltages, enabling simultaneous realization of one low-pass (LP), two BP, two HP, and one LPN/RN filtering responses from the same configuration. Each filter parameter, namely the pole angular frequency (ω o ) and quality factor (Q), can be electronically controlled and orthogonally adjusted by the corresponding LT1228 bias current I B . In special cases, the parameters of ω o and Q can be electronically controlled and independently adjusted. Each electronically adjustable VM multifunction biquadratic filter has one high input impedance and three low output impedances for independent control of BP, HP, and LPN/RN filter gains. Due to its one high input impedance and three low output impedances, each proposed filter is suitable for cascaded VM circuits without external voltage buffers. Pspice simulations are used to verify the theoretical structure analysis of each proposed LT1228-based electronically adjustable VM multifunction biquadratic filter. Furthermore, experimental tests are performed using three off-theshelf LT1228 ICs, and several passive components to verify and evaluate the performance of each proposed LT1228-based biquadratic filter.INDEX TERMS LT1228, analog circuit design, integrated circuits, voltage-mode, filters.

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Programmable 2D linear filter for video applications

Cited by 25 publications

References 4 publications

From application descriptions to hardware in seconds: a logic-based approach to bridging the gap

From application descriptions to hardware in seconds: a logic-based approach to bridging the gap

A defect-tolerant systolic array implementation for real time image processing

Two New and Improved Electronically Adjustable Voltage-Mode Multifunction Biquadratic Filters With Independent Control of Band-Pass, High-Pass, and Low-Pass/Regular Notch Filter Gains

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