Proximity Communication flip-chip package with micron chip-to-chip alignment tolerances

Sze, T.; Giere, M.; Guenin, B.M.; Nettleton, N.; Popovic, Darko; Shi, Jing; Bezuk, Steve; Ho, Ron; Drost, Robert; Douglas, D.

doi:10.1109/ectc.2009.5074130

Cited by 7 publications

(3 citation statements)

References 1 publication

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“…For the Krazo alumina ceramic substrate, the two Island die will have a greater than 25 lm alignment variation over the operating range [18]. Since this chip-to-chip misalignment was greater than could be compensated with the steering circuits, we developed a method to overcome these variations by pre-aligning and adhesively bonding the two PxC interfaces to maintain the required level of alignment.…”

Section: Package Structure and Assemblymentioning

confidence: 99%

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Sze

Popovic

Shi

et al. 2010

Microelectronics Reliability

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Section: Package Structure and Assemblymentioning

confidence: 99%

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Sze

Popovic

Shi

et al. 2010

Microelectronics Reliability

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“…There is an allocated cavity in the substrates to accommodate the bridge chip. The substrates' dimensions and the PxC technology background have been detailed earlier [8,9]. The ceramic substrate is built out of 16 alumina layers with tungsten conductors in the top layer arrayed at 180μm pitch on the chip side and at 1 mm pitch on its LGA socket side.…”

Section: Micro-spring Processingmentioning

confidence: 99%

A package demonstration with solder free compliant flexible interconnects

Shubin

Chow

Cunningham

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Flexible, stress-engineered spring interconnects are a novel technology potentially enabling room temperature assembly approaches to building highly integrated and multi-chip modules (MCMs). Such interconnects are an essential solderfree technology facilitating the MCM package diagnostics and rework. Previously, we demonstrated the performance, functionality, and reliability of compliant micro-spring interconnects under temperature cycling, humidity bias and high-current soak. Currently, we demonstrate for the first time the package with the 1st level conventional fine pitch C4 solder bump interconnects replaced by the arrays of microsprings. Dedicated CMOS integrated circuits (ICs) have been assembled onto substrates using these integrated microsprings. Metrology modules on the ICs are designed and used to characterize the connectivity and resistance of each microspring site. IntroductionCurrent trends and progress in microelectronics continue to be enabled by chip packaging technologies. As die sizes, I/O count, and power densities grow, significant challenges develop in connecting chips to their first-level packages. Additionally, ongoing developments in 3D integration and multi-chip modules (MCMs) present new opportunities for novel I/O technologies that improve performance despite severe dimensional constraints.Electronic packaging based on stress-engineered spring interconnects [3,12] can potentially improve chip testing, rework, and mechanical compliance. With conventional flipchip bonding, the rigid solder reflown microbumps can cause package failure due to excessive shear, as there is a significant CTE mismatch between a silicon integrated circuit (IC) die and the package substrate. Spring-based interconnects, on the other hand, are flexible and compliant; they present a stressfree, lead-free packaging solution for connecting an IC die to ceramic and organic substrates. They also provide rematable connections to enable a reusable, reworkable MCM platform where an ability to separate non-functional and functional die, i.e. identifying known good die (KGD), is key to enhancing assembly yield.Previously, we have realized micro-spring prototypes that meet the stringent electrical and mechanical demands of a typical modern, high-performance microprocessor package; each spring provides <100 mΩ per connection and >30 μm of compliance; spring reliability was also confirmed under 0-100°C temperature cycling, 85/85 temperature humidity bias, and a high-current soak [1][2].

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“…This paper explores these issues using simulation more extensively than had previously published work. [2] …”

Section: Introductionmentioning

confidence: 97%

Mechanical analysis and reliability enhancement of a Proximity Communication flip chip package

Guenin

Shi

2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Proximity Communication is a technology that enables high-bandwidth chip-to-chip signaling using dense arrays of metal pads that are capacitively coupled to the corresponding pads on the neighboring chip.To successfully deploy Proximity Communication requires limiting chipx-y misalignment and separation to be less than 8 µm and maintaining these tolerances over many temperature cycles. This paper examines these requirements in light of test results and detailed mechanical modeling to both understand the performance of existing package designs and to identify design modifications that lead to improved performance.

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Proximity Communication flip-chip package with micron chip-to-chip alignment tolerances

Cited by 7 publications

References 1 publication

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

A package demonstration with solder free compliant flexible interconnects

Mechanical analysis and reliability enhancement of a Proximity Communication flip chip package

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