Pseudorandom-pattern test resistance in high-performance DSP datapaths

Abstract

The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testing problem, and the associated fault detection probabilities are derived in terms of signal probability distributions. A method of calculating these distributions is described, and it is shown how these distributions can be used to predict testing problems that arise from the correlation properties of test sequences generated using linear-feedback shift registers. Finally, it is shown empirically that variance matching using associativity transformations can reduce the number of untested faults by a factor of eight over variance mismatched designs.

Redundancy and testability in digital filter datapaths

“…If the input is the carry input to the full adder, the overflow tests are and (or tests 1 and 6 if the minterms are interpreted as binary numbers). Tests 2 and 5 are also common test-resistant faults in high-order adder bits, while tests 0, 3, 6, and 7 tend to be much easier to apply [3]. Under this fault model, testing the carry logic requires five tests: the three labeled (essential) in the right half of Fig.…”

“…The test signal variance problem can be addressed by using a test signal with variance close to one, the upper limit on signal variance if the test signal is interpreted as a two's-complement number in the interval ; specific approaches are outlined in [23], [3], and [24]. One means of implementing a maximum-variance test signal is to simply use 1 bit of an LFSR to select between the maximum positive and minimum negative representable numbers.…”

“…DSP designs tend to have some very desirable test properties, chief among them good observability and controllability over large parts of the datapath. However, some designs contain faults that are strongly resistant to detection by random patterns, posing an obstacle to low-cost on-chip testing [3]. In some cases, small alterations to the design can provide enough improvement in observability or controllability to implement a built-in self-test approach that does not seriously impact circuit area or performance [4], [5].…”