PVT compensated inverter‐based OTA for low‐voltage CT sigma‐delta modulators

Aguirre, Paulo César C. de; Susin, Altamiro

doi:10.1049/el.2018.6327

Cited by 11 publications

(9 citation statements)

References 9 publications

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“…More generally, for the stabilization of G m values regarding PVT variations, some strategies are based on a feedback control loop. Variations are measured, for example, across an off‐chip resistor and will allow to adjust a biasing voltage or current thanks to the feedback, as, for example, in de Aguirre and Susin 32 . In what follows in this work, the PVT variations are corrected manually with a tuning voltage, provided that one of the previous strategies could be implemented in a similar way.…”

Section: Proposed Second Order All‐pass Topologymentioning

confidence: 99%

“…Despite their very high transconductance efficiency and bandwidth capability, inverter‐based OTA is susceptible to process, voltage, and temperature variation. To benefit the prescribed properties while remaining robust to variation is still an interesting subject discussed in state‐of‐the art 32‐34 . The approach we propose here for the design of the transconductors is to have tuning voltages to tune the values of tranconductances.…”

Section: Circuit Descriptionmentioning

confidence: 99%

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A linear group delay filter with tunable positive slope for analog signal processing

Avignon-Meseldzija

Anastasov

Milić

2021

Circuit Theory & Apps

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Summary This article describes the design of a tunable positive slope linear group delay filter dedicated to analog signal processing applications. The designed filter is composed of eight second‐order all‐pass cells which have been optimized to obtain a highly linear global group delay characteristic over a specified bandwidth for a specified dispersion. Each of these second‐order cells is designed with a dedicated Gm‐C topology to fit the ideal group delay characteristic with a high efficiency. Based on the sensitivity analysis of the topology, the possibility of tuning the group delay slope is highlighted. The design has been achieved with the ST CMOS 55 nm technology and has a maximum bandwidth of 2.5 GHz, a maximum reachable delay of 5.12 ns, and a group delay maximum variation of 2.5 ns. The positive slope of the group delay can be tuned in the range from 1.48 ns/GHz up to 2.03 ns/GHz. The concept of slope tunability is validated through post‐layout statistical analysis.

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Section: Proposed Second Order All‐pass Topologymentioning

confidence: 99%

Section: Circuit Descriptionmentioning

confidence: 99%

A linear group delay filter with tunable positive slope for analog signal processing

Avignon-Meseldzija

Anastasov

Milić

2021

Circuit Theory & Apps

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“…where V CMO1 is the common-mode output voltage of the first stage. Substituting (11) into (10), the drain current of M 12 is obtained…”

Section: Output Current Of Fvfcsmentioning

confidence: 99%

“…The operational trans-conductance amplifier (OTA) is one of the most widely used building blocks in analog design [1][2][3][4][5][6][7][8]. OTA can be used in low-voltage, low-power, and high-speed applications such as continuous-time Gm-C filters, switched-capacitor circuits, data converters, biomedical implants, signal conditioning of sensors, voltage regulators, and RF receivers [9][10][11][12][13][14][15][16][17][18][19][20]. In these applications, OTAs should have high values for DC-gain, slew rate (SR), and unity-gain bandwidth (UGBW) [21][22][23].…”

Section: Introductionmentioning

confidence: 99%

84 dB DC‐gain two‐stage class‐AB OTA

Anisheh

Abbasizadeh

Shamsi

et al. 2019

IET Circuits, Devices & Systems

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Operational trans-conductance amplifiers (OTAs) are an essential building block in analogue and mixed-signal circuits. In this study, a new two-stage class-AB OTA is proposed. The class-AB operation is obtained without extra power dissipation, and without unity-gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC-gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state-of-the-art designs.

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“…The OTA reported in [20] operates with a supply voltage of 1 V and exhibits state of the art small-signal and large-signal figures of merit. Unfortunately, most of these conventional amplifier topologies are not suited for applications requiring supply voltages lower than 0.5 V, and inverter-based [21][22][23][24][25][26] and pseudo-differential [27,28] architectures are preferred. However, an aggressive supply voltage scaling severely limits the swing of the control voltage, thus strongly limiting the effectiveness of body bias approaches to set the bias or the common mode current.…”

Section: Introductionmentioning

confidence: 99%

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Centurelli

Sala

Monsurrò

et al. 2022

JLPEA

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In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

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PVT compensated inverter‐based OTA for low‐voltage CT sigma‐delta modulators

Cited by 11 publications

References 9 publications

A linear group delay filter with tunable positive slope for analog signal processing

A linear group delay filter with tunable positive slope for analog signal processing

84 dB DC‐gain two‐stage class‐AB OTA

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

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