Q100

Abstract

In this paper, we propose Database Processing Units, or DPUs, a class of domain-specific database processors that can efficiently handle database applications. As a proof of concept, we present the instruction set architecture, microarchitecture, and hardware implementation of one DPU, called Q100. The Q100 has a collection of heterogeneous ASIC tiles that process relational tables and columns quickly and energy-efficiently. The architecture uses coarse grained in- structions that manipulate streams of data, thereby maximizing pipeline and data parallelism, and minimizing the need to time multiplex the accelerator tiles and spill inter- mediate results to memory. This work explores a Q100 de- sign space of 150 configurations, selecting three for further analysis: a small, power-conscious implementation, a high- performance implementation, and a balanced design that maximizes performance per Watt. We then demonstrate that the power-conscious Q100 handles the TPC-H queries with three orders of magnitude less energy than a state of the art software DBMS, while the performance-oriented design out- performs the same DBMS by 70X.

SMSE: A serverless platform for multimedia cloud systems

“…application-specific integrated circuits (ASICs). Google TPUs, 1 AWS Inferentia, 2 data processing units, 3 Intel quick sync video, 4 Xilinx FPGA video encoder, 5 along with various models of Nvidia GPU 6 are just a few popular mentions in this drastic shift.…”

“…application‐specific integrated circuits (ASICs). Google TPUs, 1 AWS Inferentia, 2 data processing units, 3 Intel quick sync video, 4 Xilinx FPGA video encoder, 5 along with various models of Nvidia GPU 6 are just a few popular mentions in this drastic shift. It is anticipated that the datacenters with such ASICs machines will be the cornerstone of next generation cloud computing systems.…”