Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell

Sharma, Pulkit; Bharath, K.; Gulati, Jasmine Kaur; Walia, Preet K.; Darak, Sumit J.

doi:10.1109/isvdat.2016.8064899

Cited by 2 publications

(1 citation statement)

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“…The delay and rms power calculated in this work for 1-bit SET based SRAM has been compared with the 22 nm CMOS [21] based SRAM as shown in Table 3 and Table 4. Further, the average read and write delay of standard 6T SRAM cell at 0.8V presented in this work are 34.4ps and 3.9ps as compared to 3000ps and 60ps respectively at 1V demonstrated by Sharma et al [22].…”

Section: Delay and Power Analysis For 1-bit Sram Cellmentioning

confidence: 43%

Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

Parekh

2019

IJIE

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IntroductionIntegrated circuits require high speed and low power for processing data. Scaling of technology plays an important role for improvement in the performance of an IC. By technology scaling, the performance of processor can be improved in terms of speed but the speed of a memory is lagging behind the processor speed [1]. Modern SRAM demands high density while maintaining low power consumption and high performance. Presently, the density of SRAM is increasing and it occupies 90 % of the chip area [2]. One of the solutions is to scale the transistor of the SRAM cell. Scaling of the transistor causes velocity saturation, mobility degradation, lower breakdown voltage, increased leakage currents and thus increases in leakage power [3,4]. These challenges of CMOS has motivated numerous novel device like I-MOS, NEMS switch, Spin MOSFET, spin FET, Mott FET and single electron transistor (SET) [5] for either memory or logic applications. SET is a promising and elegant device in nanoelectronics because of its ultra-low power consumption, room temperature operation, scaling potential and CMOS comparable voltage that enables SET to be interfaced with CMOS circuits. SET with a wide operating temperature range up to 130 ˚C can be successfully fabricated with a CMOS compatible back-end-of-line (BEOL) process [6]. SET based low power applications like nonvolatile memory, PLA and logic circuits can be heterogeneously integrated with CMOS circuits [7].Abstract: Heterogeneous 3D integration of single electron transistor (SET) circuits with CMOS based circuits is achieved by stacking a SET layer above CMOS IC. Low power and delay efficient circuits can be designed using SET. In this paper, we have designed and simulated 6T SRAM array operating at room temperature and at CMOS comparable voltage. Peripheral circuit like sense amplifier, decoder, write circuit and pre-charge circuit using SET have been designed for optimum performance. The stability of 6T SRAM cell is verified using N-curve method. The designed SET based 8 x 8 bit SRAM is 99.54 % power efficient, 92.19 % faster in write access time and 78.58 % faster in read access time compared to 16 nm CMOS based SRAM. The SRAM is designed to work at CMOS comparable voltage of 800 mV, which can be scaled up to 20 mV with better efficiency. The designed SRAM is tested and verified for variation in process, voltage and temperature. The maximum frequency of operation for the designed SET based SRAM with memory controller is 4 GHz.

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Section: Delay and Power Analysis For 1-bit Sram Cellmentioning

confidence: 43%

Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

Parekh

2019

IJIE

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Statistical Stability Characterization of Schmitt Trigger Based 10-T SRAM Cell Design

Sachdeva

Tomar

2020

2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

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Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell

Cited by 2 publications

References 2 publications

Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

Statistical Stability Characterization of Schmitt Trigger Based 10-T SRAM Cell Design

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