Quantifying the Effect of Guard Rings and Guard Drains in Mitigating Charge Collection and Charge Spread

A novel layout structure for the typical 6T-SRAM cell is designed to mitigate the single-event induced MBU. And three-dimensional technology computer-aided design (TCAD) numerical simulation is used to evaluate the MBU hardening performance of this novel layout structure. Compared to other layout structures, our proposed layout can effectively attenuate the single-event induced MBU in typical 6T-SRAM with little area and power penalty.

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…But this technique is applied to the deep N-well process. For the typical twin-well process, the bipolar amplification effect is more pronounced in PMOS transistors [11,12]. This will increase the charge collected by the adjacent PMOS transistors in the two adjacent SRAM cells.…”

Section: Related Workmentioning

confidence: 99%

A novel layout placement structure to mitigate the multi-bit-upset in 6T-SRAM cell

Zeng

2014

“…At layout-level, guard rings and guard bands are usually used to sink excess charge away to reduce the produced SET pulse width [2,3]. A layout hardening technique presented by Atkinson et al [4] exploits the pulse quenching effect to limit the pulse origination.…”

Section: Introductionmentioning

confidence: 99%

A DMR logic for mitigating the SET induced soft errors in combinational circuits

Zhang

Yang

et al. 2016

In this paper, a novel dual module redundancy (DMR) logic circuit structure is proposed to harden the standard cells in the large combinational circuits. Three-dimensional TCAD simulation results present that this hardening structure can ultimately eliminate the SET pulse. Based on this DMR logic circuit structure and the layout placement adjustment technique, the partial hardening approach is used to harden the large combination circuits.

“…In common CMOS process, the radiation hardened by design (RHBD) layout methods have been proposed to enhance the SET tolerance [1,2,3,4,5,6,7]. Charge sharing techniques and SETs model are used to mitigate SET effects [8,9].…”

Section: Introductionmentioning

confidence: 99%

A single-event transient hardened LDO regulator with built-in filter

Zhang

Ding

Liu

et al. 2015

A single-event transient (SET) hardened LDO using novel structure is proposed to enhance the single-event effect tolerance. The novel LDO with built-in filter can mitigate the response of the sensitive nodes of circuit. If the SET pulse current flows through the sensitive nodes, the maximum variation of the output voltage is only 15.5 mV. In addition, the transient performance is slightly dropped back as a tradeoff for the built-in filter. When the workload changes transiently between 100 µA and 100 mA in 100 ns, the undershoot is 28.4 mV and the overshoot is nearly 20 mV with imperceptible peak.