Quantitative Analysis of Multistage Switching Networks for Embedded Programmable Devices

Renzini, Francesco; Cuppini, Matteo; Mucci, Claudio; Scarselli, Eleonora Franchi; Canegallo, R.

doi:10.3390/electronics8030272

Cited by 3 publications

(2 citation statements)

References 27 publications

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“…One also finds synthesizable eFPGAs with a datapath-oriented structure [35]. Our proposed eFPGA is fully-synthesizable -soft IP as reported in Table I -as shown in [25] and the interconnection network is based on a multi-stage switching network [36]. This type of interconnection network allows full-routability and provides sustainable area overhead in small-size devices.…”

Section: Embedded Fpgasmentioning

confidence: 99%

“…This kind of network provides synthesizability and non-blocking routing features. Each CLB has 12 I/Os and 3 Basic Logic Elements [36] respectively describe the eFPGA structure and the MSSN characteristics. The computational capability of the eFPGA is about 1k equivalent-gates and this under exploitation of the occupied area -100k eq.…”

Section: B Embedded Fpga Sub-systemmentioning

confidence: 99%

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A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

Renzini

Mucci

Rossi

et al. 2020

IEEE Trans. Circuits Syst. I

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This paper proposes a reconfigurable System-on-Chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at a lower power consumption and higher responsiveness than with processor-based execution. To the best of the authors' knowledge this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating Bipolar, CMOS and DMOS devices, typically featuring a small amount of metal layers when compared to traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable, since the eFPGA is based on a soft-core approach. The paper presents the results of integrating an eFPGA with a computational capability of 1k equivalent gates in STMicroelectronics 90 nm BCD technology featuring five metal layers and high-k transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20-27% area overhead, but has a straightforward benefit in terms of energy consumption which proves reduced from about 10× to 800×. In terms of latency, the eFPGA implementation allows a gain from 8× to 145× comparing the pure cycles count.

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Section: Embedded Fpgasmentioning

confidence: 99%

Section: B Embedded Fpga Sub-systemmentioning

confidence: 99%