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Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific optimization, in terms of DSP blocks, technology options and floorplan requirements. For that, in this paper, we analyse a soft-core eFPGA template based on MultiStage Switching Network which couples high flexibility with a modular design approach based on the regular replication of few simple switch modules for the programmable routing. Implementation on 65nm technology showed the existence of a significantly wide design space which allows to quickly optimize the device for area, speed and/or leakage power. Results show that depending on architectural and technology options adopted, performance can vary in terms of area (~50%), speed (+/-30%) and leakage (~90%) with respect to a reference design.

Nowadays Smart Power technologies are demanding smarter devices to give the opportunity of end-user customizations to reach best-in-class efficiency in applications such as sensing and power conversions. Reconfigurable devicesin the form of embedded FPGA (eFPGA) -can represent an effective solution to address such demand. Differently from CMOS world, where reconfigurable technologies have been widely proposed in the last two decades to couple flexibility and NRE costs reduction, eFPGAs targeting Smart Power applications is a new challenge that we can face today thanks to recent improvement of the digital capabilities of such technologies. In this paper we explore the implementation of a soft-core eFPGA tailored for Smart Power applications targeting STMicroelectronics BCD9s 0.11 µm technology. Area-optimized and speed-optimized implementations prove the existence of a significant design space, both in terms of area (~15%) and speed (~50%) variation. A set of benchmarking applications representative of different smart power fields (sigma-delta modulation, power management and motion control) have been mapped on a 16 CLBs eFPGA; the performance are discussed showing the potential added-value provided by reconfigurability.

This paper analyzes the properties of a class of congestion-free multistage switching networks (MSSNs) are butterfly-based and suitable for embedded programmable devices, which require sustaining static multicast connectivity. These MSSNs are fully synthesizable and enable the design of programmable IPs with typical size in the order of 1 KLUT, coupling flexibility with fast turn-around time. The non-blocking property for static connection of this class of MSSN is discussed. Our analysis shows pros and cons of adopting radix-2 or radix-4 MSSN structures, as well as the impact of bypass-paths to make the network fully hierarchical and locality-aware thanks also to a dedicated programming strategy. Implementation experiments carried out on STM CMOS 65 nm technology show the availability of various area-speed trade-offs, resulting in a range of ≃2× in frequency and a range of ≃ 4 × in area. Depending on the specific application-field, an optimal interconnect definition is thus achieved without compromising the routability properties. In this respect, the paper proposes a simplified application-driven model for evaluation of the best MSSN, including bypass-adoption and radix selection.

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