This paper presents an Analog Front-End for integrated Wake-Up Radios. The proposed Analog Front-End is composed of an envelope detector, a Schmitt trigger and a biasing block and has three distinctive features: i) clockless solution, which does not require an always-on oscillator; ii) an envelope detector with band-pass response which leads to smaller capacitance, thus easier integration, and low-frequency noise suppression; iii) temperature compensated biasing scheme. An active scheme for the detector is used based on MOSFETs operated in the subthreshold region with a self-biased topology. Advantages and drawbacks of the proposed architecture are analyzed. A prototype was fabricated in the STMicroelectronics 90-nm BCD technology. The overall power consumption, excluding the biasing block, is 36 nW at 1.2 V. A 10 -3 Bit Error Rate is measured with a 771-MHz, 2-kbit/s OOK modulated input signal with -46 dBm power at room temperature and at -20 °C, and with almost -43 dBm power at 60 °C.

This paper proposes a reconfigurable System-on-Chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at a lower power consumption and higher responsiveness than with processor-based execution. To the best of the authors' knowledge this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating Bipolar, CMOS and DMOS devices, typically featuring a small amount of metal layers when compared to traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable, since the eFPGA is based on a soft-core approach. The paper presents the results of integrating an eFPGA with a computational capability of 1k equivalent gates in STMicroelectronics 90 nm BCD technology featuring five metal layers and high-k transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20-27% area overhead, but has a straightforward benefit in terms of energy consumption which proves reduced from about 10× to 800×. In terms of latency, the eFPGA implementation allows a gain from 8× to 145× comparing the pure cycles count.

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This paper analyzes the properties of a class of congestion-free multistage switching networks (MSSNs) are butterfly-based and suitable for embedded programmable devices, which require sustaining static multicast connectivity. These MSSNs are fully synthesizable and enable the design of programmable IPs with typical size in the order of 1 KLUT, coupling flexibility with fast turn-around time. The non-blocking property for static connection of this class of MSSN is discussed. Our analysis shows pros and cons of adopting radix-2 or radix-4 MSSN structures, as well as the impact of bypass-paths to make the network fully hierarchical and locality-aware thanks also to a dedicated programming strategy. Implementation experiments carried out on STM CMOS 65 nm technology show the availability of various area-speed trade-offs, resulting in a range of ≃2× in frequency and a range of ≃ 4 × in area. Depending on the specific application-field, an optimal interconnect definition is thus achieved without compromising the routability properties. In this respect, the paper proposes a simplified application-driven model for evaluation of the best MSSN, including bypass-adoption and radix selection.

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