Quantum circuit optimizations for NISQ architectures

Nash, Beatrice; Gheorghiu, Vlad; Mosca, Michele

doi:10.1088/2058-9565/ab79b1

Cited by 102 publications

(136 citation statements)

References 18 publications

(47 reference statements)

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“…• When there are topological constraints among addressable qubits, is there any efficient algorithm to parallelize CNOT circuits? Towards this, a recent work [13] offers an algorithm to reduce its size to O(n 2 ) under constraints, but how to decrease its depth is still unknown.…”

Section: Conclusion and Open Questionsmentioning

confidence: 99%

“…For circuit size, Patel, Markov, and Hayes [2] proved that each n-qubit CNOT circuit can be synthesized with O(n 2 / log n) CNOT gates and this bound is asymptotically tight. When topological constraints -i.e., there is limited two-qubit connectivity among their addressable qubits -are taken into consideration, synthesis algorithms have been designed by Kissinger-de Griend [12] and Nash-Gheorghiu-Mosca [13] to build circuits of size O(n 2 ). For circuit depth, Moore and Nilsson [1] proved that given O(n 2 ) ancillae, any n-qubit CNOT circuit can be parallelized into O(log n) depth.…”

Section: Introductionmentioning

confidence: 99%

“…At a high level, Global Constrained Minimization (GCM) aims to find the optimal size or depth under certain topological constraints S, where CNOT gate with control i and target j is legal iff (i, j) ∈ S. This restriction is common in existing quantum devices [27,28] and CNOT circuit optimization on such devices has been discussed [13,12]. The Local Size Minimization (LSM) aims to optimize the size of a selected part of the circuit while leaving other parts unchanged.…”

Section: Introductionmentioning

confidence: 99%

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Optimal Space-Depth Trade-Off of CNOT Circuits in Quantum Logic Synthesis

Jiang

Sun

Teng

et al. 2020

Proceedings of the Fourteenth Annual ACM-SIAM Symposium on Discrete Algorithms

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Due to the decoherence of the state-of-the-art physical implementations of quantum computers, it is essential to parallelize the quantum circuits to reduce their depth. Two decades ago, Moore and Nilsson [1] demonstrated that additional qubits (or ancillae) could be used to design "shallow" parallel circuits for quantum operators. They proved that any n-qubit CNOT circuit could be parallelized to O(log n) depth, with O(n 2 ) ancillae. However, the near-term quantum technologies can only support limited amount of qubits, making space-depth trade-off a fundamental research subject for quantum-circuit synthesis.In this work, we establish an asymptotically optimal space-depth trade-off for the design of CNOT circuits. We prove that for any m ≥ 0, any n-qubit CNOT circuit can be parallelized to O max log n, n 2 (n+m) log(n+m) depth, with m ancillae. We show that this bound is tight by a counting argument, and further show that even with arbitrary two-qubit quantum gates to approximate CNOT circuits, the depth lower bound still meets our construction, illustrating the robustness of our result. Our work improves upon two previous results, one by Moore and Nilsson [1] for O(log n)-depth quantum synthesis, and one by Patel, Markov, and Hayes [2] for m = 0: for the former, we reduce the need for ancillae by a factor of log 2 n by showing that m = O(n 2 / log 2 n) additional qubits -which is asymptotically optimal -suffice to build O(log n)-depth, O(n 2 / log n)-size CNOT circuits; for the later, we reduce the depth by a factor of n to the asymptotically optimal bound O n log n . Our results can be directly extended to stabilizer circuits using an earlier result by Aaronson and Gottesman [3]. In addition, we provide relevant hardness evidence for synthesis optimization of CNOT circuits in term of both size and depth.

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Section: Conclusion and Open Questionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Optimal Space-Depth Trade-Off of CNOT Circuits in Quantum Logic Synthesis

Jiang

Sun

Teng

et al. 2020

Proceedings of the Fourteenth Annual ACM-SIAM Symposium on Discrete Algorithms

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“…each one of them is capable of applying CZ gates upon any pair of qubits it holds; this idealisation can be accounted for at a later stage. Recent research has provided automated methods for efficiently simulating any circuit on topologically constrained QPUs, either by finding the least amount of qubit swappings required [33] or by redesigning the circuit from scratch using, for instance, Steiner trees [34,35]. In practice, any of these methods may be used to simulate each of the circuits our algorithm (see Section III) allocates to each QPU, so the QPUs may actually be topologically constrained.…”

Section: The Circuit Distribution Problemmentioning

confidence: 99%

Automated distribution of quantum circuits via hypergraph partitioning

Andrés-Martínez

Heunen

2019

Phys. Rev. A

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Quantum algorithms are usually described as monolithic circuits, becoming large at modest input size. Near-term quantum architectures can only manage a small number of qubits. We develop an automated method to distribute quantum circuits over multiple agents, minimising quantum communication between them. We reduce the problem to hypergraph partitioning and then solve it with state-of-the-art optimisers. This makes our approach useful in practice, unlike previous methods. Our implementation is evaluated on five quantum circuits of practical relevance.PACS numbers: 03.67.Ac; 03.67.Lx I. INTRODUCTIONQuantum computation [1-3] employs the laws of quantum mechanics to design systems capable of outperforming classical computers in certain problems [4][5][6]. Over the past couple of decades, this idea has rapidly developed from theoretical results into actual quantum technology [7][8][9].Although there are other approaches [10], the dominant way to present a quantum algorithm is as a quantum circuit [11]: a description of how quantum devices, chosen from a fixed finite set, are applied to different parts of the input system; see Figure 1 for an example. Each of the 'wires' that quantum devices act upon typically consist of a two level quantum system called a quantum bit or qubit. The qubit count grows with the input size, and for relevant problems such as the unique shortest vector problem (with applications in cryptography [12]) the circuit grows large: lattice dimension 3 already requires 842 qubits and 95,624 gates [13].Near-term quantum computing architectures are not capable of executing such large circuits. We are currently entering the era of Noisy Intermediate-Scale Quantum (NISQ) technology [14], being able to fabricate small quantum computing units (QPU for short) ranging from 10 to almost 100 qubits. Much effort is being dedicated to further increase the number of qubits that QPUs can manage, but as the number of qubits grows, the challenge of addressing each qubit individually and shielding them from unwanted interactions and decoherence rapidly becomes unmanageable [15]. To scale up beyond this point, researchers are proposing distributed quan-

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“…Recently, a novel reverse traversal technique is proposed in [13] to choose the initial mapping with the consideration of the whole circuit. The second approach is to utilize unitary matrix decomposition algorithms to reconstruct a quantum circuit from scratch while preserving the functionality of the input circuit [16,12]. The third one is to convert the quantum circuit transformation problem to some existing problems like AI planning and constraint programming and use ready-made tools for these problems to find acceptable results [4,23].…”

Section: Introductionmentioning

confidence: 99%

Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search

Zhou

Feng

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Quantum algorithm design usually assumes access to a perfect quantum computer with ideal properties like full connectivity, noise-freedom and arbitrarily long coherence time. In Noisy Intermediate-Scale Quantum (NISQ) devices, however, the number of qubits is highly limited and quantum operation error and qubit coherence are not negligible. Besides, the connectivity of physical qubits in a quantum processing unit (QPU) is also strictly constrained. Thereby, additional operations like SWAP gates have to be inserted to satisfy this constraint while preserving the functionality of the original circuit. This process is known as quantum circuit transformation. Adding additional gates will increase both the size and depth of a quantum circuit and therefore cause further decay of the performance of a quantum circuit. Thus it is crucial to minimize the number of added gates. In this paper, we propose an efficient method to solve this problem. We first choose by using simulated annealing an initial mapping which fits well with the input circuit and then, with the help of a heuristic cost function, stepwise apply the best selected SWAP gates until all quantum gates in the circuit can be executed. Our algorithm runs in time polynomial in all parameters including the size and the qubit number of the input circuit, and the qubit number in the QPU. Its space complexity is quadratic to the number of edges in the QPU. Experimental results on extensive realistic circuits confirm that the proposed method is efficient and can reduce by 57% on average the size of the output circuits when compared with the state-of-the-art algorithm on the most recent IBM quantum device viz. IBM Q20 (Tokyo).

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Quantum circuit optimizations for NISQ architectures

Cited by 102 publications

References 18 publications

Optimal Space-Depth Trade-Off of CNOT Circuits in Quantum Logic Synthesis

Optimal Space-Depth Trade-Off of CNOT Circuits in Quantum Logic Synthesis

Automated distribution of quantum circuits via hypergraph partitioning

Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search

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