Quantum simulations of electrostatics in Si cylindrical nanowire pinch-off nFETs and pFETs with a homogeneous channel including strain and arbitrary crystallographic orientations

Pham, Anh-Tuan; Sorée, Bart; Magnus, Wim; Jungemann, C.; Meinerzhagen, B.; Pourtois, Geoffrey

doi:10.1109/ulis.2011.5757989

Cited by 2 publications

(1 citation statement)

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“…Thus for JL transistors, the QCEs would be effective in a device with a relatively lower cross section than 7 nm or less [46]. Quantum analysis by several authors [29,36,47] have also shown the improvement in gate controllability in JL transistors with a reduction of channel doping. Therefore, with the inclusion of quantum effects, the current drive may be lower than suggested by our work.…”

Section: Simulationmentioning

confidence: 99%

Revisiting the doping requirement for low power junctionless MOSFETs

Parihar

Kranti

2014

Semicond. Sci. Technol.

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In this work, we revisit the requirement of higher channel doping ( 10 19 cm −3 ) in junctionless (JL) double gate MOSFETs. It is demonstrated that moderately doped (10 18 cm −3 ) ultra low power (ULP) JL transistors perform significantly better than heavily doped (10 19 cm −3 ) devices. JL MOSFETs with moderate doping results in the spreading out of carriers across the entire silicon film instead of being localized at the center of the film. This improves gate controllability leading to higher on-off current ratio and lower intrinsic delay for ULP subthreshold logic applications. Additional benefits of using a channel doping concentration of 10 18 cm −3 instead of conventional heavily doped design is the significant reduction in threshold voltage sensitivity values (by ∼70-90%) with respect to film thickness and gate oxide thickness. Further improvement in ULP performance metrics can be achieved by limiting the source/drain implantation away from the gate edge. This design, specifically for ULP, allows the requirement of gate workfunction to be reduced from p + -poly (∼ 5.1 eV) to near about midgap values (∼ 4.8 eV). On-off current ratio and intrinsic delay for optimized JL devices are compared for low standby power projections of the technological roadmap. A 6T-SRAM cell operating at 0.8 V with 25 nm JL devices exhibits a static noise margin of 151 mV with gate workfunction offset of 0.2 eV with respect to midgap value (4.72 eV). The results highlight new viewpoints for realizing improved low power JL transistors.

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